Patents by Inventor Masayoshi Koike

Masayoshi Koike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070141741
    Abstract: In a semiconductor laminated structure, a base substrate has a nitride semiconductor crystal plane in an upper surface thereof. A growth blocking film encloses a flow-through pattern which is extended horizontally on the base substrate at a predetermined interval. A nitride semiconductor crystal layer is formed on the base substrate to contact the upper surface thereof between regions of the flow-through pattern and covers the grow blocking film. The semiconductor laminated structure is employed to obtain a nitride semiconductor crystal layer, nitride semiconductor crystal substrate and nitride semiconductor device exhibiting fewer defects and high quality.
    Type: Application
    Filed: August 17, 2006
    Publication date: June 21, 2007
    Inventors: Hyo Suh, Masayoshi Koike, Sung Jang, Soo Lee, Jong Yang, Jin Hong
  • Publication number: 20070105259
    Abstract: A method for growing a high quality indium gallium nitride by metal organic chemical vapor deposition (MOCVD) is provided. In the method, the indium gallium nitride grows at a growth rate of at least about 1.5 nm/min at a temperature of at least about 800° C. while an internal pressure of an MOCVD reactor is maintained at about 400 mbar or less.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 10, 2007
    Inventors: Jong Won, Masayoshi Koike, Jae Han, Seong Lee
  • Patent number: 7186579
    Abstract: A semiconductor laser comprises a sapphire substrate, an AlN buffer layer, Si-doped GaN n-layer, Si-doped Al0.1Ga0.9N n-cladding layer, Si-doped GaN n-guide layer, an active layer having multiple quantum well (MQW) structure in which about 35 ? in thickness of GaN barrier layer 62 and about 35 ? in thickness of Ga0.95In0.05N well layer 61 are laminated alternately, Mg-doped GaN p-guide layer, Mg-doped Al0.25Ga0.75N p-layer, Mg-doped Al0.1Ga0.9N p-cladding layer, and Mg-doped GaN p-contact layer are formed successively thereon. A ridged hole injection part B which contacts to a ridged laser cavity part A is formed to have the same width as the width w of an Ni electrode. Because the p-layer has a larger aluminum composition, etching rate becomes smaller and that can prevent from damaging the p-guide layer in this etching process.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: March 6, 2007
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Takashi Hatano, Sho Iwayama, Masayoshi Koike
  • Publication number: 20070012940
    Abstract: The invention relates to a wavelength-convertible LED package including a package substrate having a lead frame, and an LED mounted on the package substrate and electrically connected to the lead frame. The wavelength-convertible LED package also includes a low refractive index region surrounding the LED, having a first refractive index, and a high refractive index layer formed on the low refractive index region, having a rough pattern on an upper surface thereof and a second refractive index higher than the first refractive index. The wavelength-convertible LED package further includes a resin part containing phosphor for converting the wavelength of light emitted from the LED, having a third refractive index lower than the second refractive index.
    Type: Application
    Filed: July 12, 2006
    Publication date: January 18, 2007
    Inventors: Hyo Suh, Hee Park, Masayoshi Koike
  • Patent number: 7163876
    Abstract: In the epitaxial growth process in which each growth region D is zoned by a mask 2 formed in grid pattern, because a consumption region C of the Group III nitride compound semiconductor is formed in the central portion of each band of the mask 2 between each adjacent edge portion of the growth region D, Group III or Group V raw material is never unnecessarily supplied to the edge portion of the growth region D. As a result, difference of Group III or Group V rare material supply amount to the edge portion and central portion of the device formation region D is suppressed and the edge portion of the device region may not be convexity.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: January 16, 2007
    Assignees: Toyoda Gosei Co., Ltd, Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Seiji Nagai, Masayoshi Koike, Kazuyoshi Tomita
  • Publication number: 20070007541
    Abstract: The invention relates to a nitride light emitting device including first and second conductivity type nitride layers and a plurality of active regions emitting light of different wavelength. The active regions are sequentially formed between the first and the second conductivity type nitride layers. The active regions include at least one first active region having a plurality of first quantum barrier layers and quantum well layers, and a second active region emitting light of a wavelength larger than that of the first active region. The second active region has a plurality of second quantum barrier layers and at least one discontinuous quantum well structure formed between the plurality of second quantum barrier layers. The discontinuous quantum well structure comprises a plurality of quantum dots or crystallites.
    Type: Application
    Filed: January 13, 2006
    Publication date: January 11, 2007
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Min Kim, Kyeong Min, Masayoshi Koike
  • Publication number: 20060292718
    Abstract: The present invention provides methods for manufacturing a nitride layer and a vertical nitride semiconductor light emitting device. In manufacturing the nitride layer according to the invention, a sapphire substrate is prepared. A buffer layer made of a material having a melting point and a thermal conductivity higher than those of nitride is formed on the sapphire substrate. Also, the nitride layer is formed on the buffer layer. Then a laser beam is irradiated to an underside of the sapphire substrate to remove the nitride layer. According to the invention, the nitride layer is made of a material having a composition expressed by AlxInyGa(1-x-y)N, where 0?x?1, 0?y?1, and 0?x+y?1. In addition, the buffer layer is made of SiC.
    Type: Application
    Filed: April 25, 2006
    Publication date: December 28, 2006
    Inventors: Hee Park, Masayoshi Koike, Kyeong Min
  • Publication number: 20060286777
    Abstract: In a method for fabricating a nitride-based compound layer, first, a GaN substrate is prepared. A mask layer with a predetermined pattern is formed on the GaN substrate to expose a partial area of the GaN substrate. Then a buffer layer is formed on the partially exposed GaN substrate. The buffer layer is made of a material having a 10% or less lattice mismatch with GaN. Thereafter, the nitride-based compound is grown laterally from a top surface of the buffer layer toward a top surface of the mask layer and the nitride-based compound layer is vertically grown to a predetermined thickness. Also, the mask layer and the buffer layer are removed via wet-etching to separate the nitride-based compound layer from the GaN substrate.
    Type: Application
    Filed: June 21, 2006
    Publication date: December 21, 2006
    Inventors: Soo Lee, Cheol Kim, Jaeun Yoo, Sung Jang, Masayoshi Koike
  • Publication number: 20060267026
    Abstract: The invention relates to a monolithic white light emitting device using wafer bonding or metal bonding. In the invention, a conductive submount substrate is provided. A first light emitter is bonded onto the conductive submount substrate by a metal layer. In the first light emitter, a p-type nitride semiconductor layer, a first active layer, an n-type nitride semiconductor layer and a conductive substrate are stacked sequentially from bottom to top. In addition, a second light emitter is formed on a partial area of the conductive substrate. In the second light emitter, a p-type AlGaInP-based semiconductor layer, an active layer and an n-type AlGaInP-based semiconductor layer are stacked sequentially from bottom to top. Further, a p-electrode is formed on an underside of the conductive submount substrate and an n-electrode is formed on a top surface of the n-type AlGaInP-based semiconductor layer.
    Type: Application
    Filed: May 31, 2006
    Publication date: November 30, 2006
    Inventors: Min Kim, Masayoshi Koike, Kyeong Min, Myong Cho
  • Publication number: 20060268955
    Abstract: The invention provides a high-quality vertical semiconductor light emitting device having fewer cracks and a manufacturing method thereof. In the vertical semiconductor light emitting device, an Si—Al alloy substrate is prepared. Then a p-type group III-V compound semiconductor layer is formed on the Si—Al alloy substrate. An active layer is formed on the p-type group III-V compound semiconductor layer. Also, an n-type group III-V compound semiconductor layer is formed on the active layer.
    Type: Application
    Filed: May 23, 2006
    Publication date: November 30, 2006
    Inventors: Myong Cho, Masayoshi Koike, Kyeong Min, Se Ahn, Hee Park
  • Patent number: 7141444
    Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/mesa such that layer different from the first Group III nitride compound semiconductor layer 31 is exposed at the bottom portion of the trench. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, laterally, with a top surface of the mesa and a sidewall/sidewalls of the trench serving as a nucleus, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. Etching may be performed until a cavity portion is provided in the substrate.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: November 28, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Yuta Tezen, Hiroshi Yamashita, Seiji Nagai, Toshio Hiramatsu
  • Patent number: 7138286
    Abstract: A light-emitting semiconductor device (10) consecutively includes a sapphire substrate (1), an AlN buffer layer (2), a silicon (Si) doped GaN n+-layer (3) of high carrier (n-type) concentration, a Si-doped (Alx3Ga1-x3)y3In1-y3N n+-layer (4) of high carrier (n-type) concentration, a zinc (Zn) and Si-doped (Alx2Ga1-x2)y2In1-y2N emission layer (5), and a Mg-doped (Alx1Ga1-x1)y1In1-y1N p-layer (6). The AlN layer (2) has a 500 ? thickness. The GaN n+-layer (3) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The n+-layer (4) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The emission layer (5) has about a 0.5 ?m thickness. The p-layer 6 has about a 1.0 ?m thickness and a 2×1017/cm3 hole concentration. Nickel electrodes (7, 8) are connected to the p-layer (6) and n+-layer (4), respectively. A groove (9) electrically insulates the electrodes (7, 8).
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: November 21, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Katsuhide Manabe, Hisaki Kato, Michinari Sassa, Shiro Yamazaki, Makoto Asai, Naoki Shibata, Masayoshi Koike
  • Publication number: 20060216914
    Abstract: The invention provides a method of growing a non-polar a-plane gallium nitride. In the method, first, an r-plane substrate is prepared. Then, a low-temperature nitride-based nucleation layer is deposited on the substrate. Finally, the non-polar a-plane gallium nitride is grown on the nucleation layer. In growing the non-polar a-plane gallium nitride, a gallium source is supplied at a flow rate of about 190 to 390 ?mol/min and the flow rate of a nitrogen source is set to produce a V/III ratio of about 770 to 2310.
    Type: Application
    Filed: March 3, 2006
    Publication date: September 28, 2006
    Applicants: Samsung Electro-Mechanics Co., Ltd., The University of Tokushima
    Inventors: Soo Lee, Rak Choi, Naoi Yoshiki, Sakai Shiro, Masayoshi Koike
  • Patent number: 7112243
    Abstract: The present invention provides a method for producing a Group III nitride compound semiconductor, which method permits only minimal reaction of the semiconductor with a hetero-substrate during epitaxial growth and induces no cracks in the Group III nitride compound semiconductor even when the semiconductor is cooled to room temperature. The method includes a buffer layer formation step for forming a gas-etchable buffer layer on the hetero-substrate, and a semiconductor formation step for epitaxially growing the Group III nitride compound semiconductor on the buffer layer through a vapor phase growth method, wherein at least a portion of the buffer layer is gas-etched during or after the semiconductor formation step.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: September 26, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Shiro Yamazaki
  • Patent number: 7084421
    Abstract: A light-emitting semiconductor device provides an active layer which comprises thirteen (13) layers that includes six (6) pairs of quantum barrier layers made of Al0.95In0.05N and quantum well layers made of Al0.70In0.30N, which are laminated together alternately. The semiconductor device may also comprise a quantum well layer having a high composition ratio of indium (In). Forming the quantum barrier layer and the quantum well layer to have a high composition ratio of indium (In) increases the lattice constant of the active layer of the semiconductor device.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: August 1, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Shiro Yamazaki, Akira Kojima
  • Publication number: 20060148186
    Abstract: A method and apparatus for manufacturing a nitride based single crystal substrate. The method includes placing a preliminary substrate on a susceptor installed in a reaction chamber; growing a nitride single crystal layer on the preliminary substrate; and irradiating a laser beam to separate the nitride single crystal layer from the preliminary substrate under the condition that the preliminary substrate is placed in the reaction chamber.
    Type: Application
    Filed: September 6, 2005
    Publication date: July 6, 2006
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Soo Min Lee, Masayoshi Koike, Kyeong Ik Min, Cheol Kyu Kim, Sung Hwan Jang, Min Ho Kim
  • Patent number: 7063997
    Abstract: A process for producing a nitride semiconductor light-emitting device includes the steps of preparing a substrate, growing a p-type nitride semiconductor layer on the substrate by the MOCVD process using hydrazine-based gas as a nitrogen precursor and N2 gas as a carrier gas, forming an active layer on the p-type nitride semiconductor layer, forming an n-type conductive nitride semiconductor layer on the active layer, and forming p- and n-electrodes in electrical connection with the p- and n-type nitride semiconductors, respectively.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: June 20, 2006
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dong Hyun Cho, Masayoshi Koike, Hun Joo Hahm
  • Publication number: 20060118821
    Abstract: A light-emitting semiconductor device (10) consecutively includes a sapphire substrate (1), an AlN buffer layer (2), a silicon (Si) doped GaN n+-layer (3) of high carrier (n-type) concentration, a Si-doped (Alx3Ga1-x3)y3In1-y3N n+-layer (4) of high carrier (n-type) concentration, a zinc (Zn) and Si-doped (Alx2Ga1-x2)y2In1-y2N emission layer (5), and a Mg-doped (Alx1Ga1-x1)y1In1-y1N p-layer (6). The AlN layer (2) has a 500 ? thickness. The GaN n+-layer (3) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The n+-layer (4) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The emission layer (5) has about a 0.5 ?m thickness. The p-layer 6 has about a 1.0 ?m thickness and a 2×1017/cm3 hole concentration. Nickel electrodes (7, 8) are connected to the p-layer (6) and n+-layer (4), respectively. A groove (9) electrically insulates the electrodes (7, 8).
    Type: Application
    Filed: January 10, 2006
    Publication date: June 8, 2006
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Katsuhide Manabe, Hisaki Kato, Michinari Sassa, Shiro Yamazaki, Makoto Asai, Naoki Shibata, Masayoshi Koike
  • Patent number: 7045829
    Abstract: A Group III nitride compound semiconductor includes a multiple layer structure having an emission layer between an n-type cladding layer and a p-type cladding layer. The n-type cladding layer may be below the emission layer, having been formed on another n-type layer which was formed over a buffer Layer and a sapphire substrate. The emission layer has a thickness which is wider than the diffusion length of holes within the emission layer. The n-type cladding layer is doped with a donor impurity and has a lattice constant Substantially equal to a lattice constant of the emission layer. The p-type cladding layer is doped with an acceptor impurity and has a forbidden band sufficiently wider than the forbidden band of the emission layer in ordor to confine electrons injected into the emission layer.
    Type: Grant
    Filed: July 23, 1996
    Date of Patent: May 16, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Shinya Asami
  • Publication number: 20060091408
    Abstract: Disclosed are a nitride based semiconductor device, including a high-quality GaN layer formed on a silicone substrate, and a process for preparing the same. A nitride based semiconductor device in accordance with the present invention comprises a plurality of nanorods aligned and formed on the silicone substrate in the vertical direction; an amorphous matrix layer filling spaces between nanorods so as to protrude some upper portion of the nanorods; and a GaN layer formed on the matrix layer.
    Type: Application
    Filed: August 16, 2005
    Publication date: May 4, 2006
    Inventors: Min Kim, Masayoshi Koike, Kyeong Min, Seong Lee, Sung Jang