Patents by Inventor Masayoshi Koike

Masayoshi Koike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7001790
    Abstract: A light-emitting semiconductor device (10) consecutively includes a sapphire substrate (1), an AlN buffer layer (2), a silicon (Si) doped GaN n+-layer (3) of high carrier (n-type) concentration, a Si-doped (Alx3Ga1-x3)y3In1-y3N n+-layer (4) of high carrier (n-type) concentration, a zinc (Zn) and Si-doped (Alx2Ga1-x2)y2In1-y2N emission layer (5), and a Mg-doped (Alx1Ga1-x1)y1In1-y1N p-layer (6). The AlN layer (2) has a 500 ? thickness. The GaN n+-layer (3) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The n+-layer (4) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The emission layer (5) has about a 0.5 ?m thickness. The p-layer 6 has about a 1.0 ?m thickness and a 2×1017/cm3 hole concentration. Nickel electrodes (7, 8) are connected to the p-layer (6) and n+-layer (4), respectively. A groove (9) electrically insulates the electrodes (7, 8).
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: February 21, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Katsuhide Manabe, Hisaki Kato, Michinari Sassa, Shiro Yamazaki, Makoto Asai, Naoki Shibata, Masayoshi Koike
  • Patent number: 6979584
    Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/post. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, from a top surface of the post and a sidewall/sidewalls of the trench serving as a nucleus for epitaxial growth, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. As a result, a region having less threading dislocations is formed at the buried trench.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: December 27, 2005
    Assignee: Toyoda Gosei Co, Ltd.
    Inventors: Masayoshi Koike, Yuta Tezen, Toshio Hiramatsu
  • Patent number: 6962828
    Abstract: A novel light-emitting device includes a saphire substrate with a light-emitting layer comprising InXGa1?XN, where the critical value of the indium mole fraction X is determined by a newly derived relationship between the indium mole fraction X and the wavelength ? of emitted light.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: November 8, 2005
    Assignees: Toyoda Gosei Co., Ltd.
    Inventors: Norikatsu Koide, Masayoshi Koike, Shiro Yamasaki, Isamu Akasaki, Hiroshi Amano
  • Publication number: 20050241571
    Abstract: A method of growing a nitride single crystal layer, and a method of manufacturing a light emitting device using the method are disclosed. The method of growing a nitride single crystal layer comprises the steps of preparing a silicon substrate having an upper surface of a crystal plane (111), forming a buffer layer having the formula of SixGe1-x, (where 0<x?1) on the upper surface of the silicon substrate, and forming a nitride single crystal on the buffer layer. Also, a nitride light emitting device using the method manufactured by the method, and a method of manufacturing the same are disclosed.
    Type: Application
    Filed: December 9, 2004
    Publication date: November 3, 2005
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Min Kim, Masayoshi Koike, Hun Hahm
  • Publication number: 20050224834
    Abstract: A light-emitting semiconductor device (10) consecutively includes a sapphire substrate (1), an AlN buffer layer (2), a silicon (Si) doped GaN n+-layer (3) of high carrier (n-type) concentration, a Si-doped (Alx3Ga1-x3)y3In1-y3N n+-layer (4) of high carrier (n-type) concentration, a zinc (Zn) and Si-doped (Alx2Ga1-x2)y2In1-y2N emission layer (5), and a Mg-doped (Alx1Ga1-x1)y1In1-y1N p-layer (6). The AlN layer (2) has a 500 ? thickness. The GaN n+-layer (3) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The n+-layer (4) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The emission layer (5) has about a 0.5 ?m thickness. The p-layer 6 has about a 1.0 ?m thickness and a 2×1017/cm3 hole concentration. Nickel electrodes (7, 8) are connected to the p-layer (6) and n+-layer (4), respectively. A groove (9) electrically insulates the electrodes (7, 8).
    Type: Application
    Filed: June 3, 2005
    Publication date: October 13, 2005
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Katsuhide Manabe, Hisaki Kato, Michinari Sassa, Shiro Yamazaki, Makoto Asai, Naoki Shibata, Masayoshi Koike
  • Publication number: 20050221526
    Abstract: A process for producing a nitride semiconductor light-emitting device includes the steps of preparing a substrate, growing a p-type nitride semiconductor layer on the substrate by the MOCVD process using hydrazine-based gas as a nitrogen precursor and N2 gas as a carrier gas, forming an active layer on the p-type nitride semiconductor layer, forming an n-type conductive nitride semiconductor layer on the active layer, and forming p- and n-electrodes in electrical connection with the p- and n-type nitride semiconductors, respectively.
    Type: Application
    Filed: July 20, 2004
    Publication date: October 6, 2005
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dong Cho, Masayoshi Koike, Hun Hahm
  • Publication number: 20050218416
    Abstract: Provided are a nitride semiconductor light-emitting device comprising a polycrystalline or amorphous substrate made of AlN; a plurality of dielectric patterns formed on the AlN substrate and having a stripe or lattice structure; a lateral epitaxially overgrown-nitride semiconductor layer formed on the AlN substrate having the dielectric patterns by Lateral Epitaxial Overgrowth; a first conductive nitride semiconductor layer formed on the nitride semiconductor layer; an active layer formed on the first conductive nitride semiconductor layer; and a second conductive nitride semiconductor layer formed on the active layer; and a process for producing the same.
    Type: Application
    Filed: July 26, 2004
    Publication date: October 6, 2005
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dong Cho, Masayoshi Koike, Yuji Imai, Min Kim, Bang Oh, Hun Hahm
  • Patent number: 6946788
    Abstract: A light-emitting element has a light-emitting layer and at lease one light-extracting portion. At least a partial part of the light-extracting portion is formed into a concave or convex surface for enhancing the efficiency of extracting light. Another light-emitting element has a light-emitting layer and a concave or convex surface for reflecting light emitted from the light-emitting layer toward one or more other surfaces of the light-emitting element through an inside of the light-emitting element.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: September 20, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yoshinobu Suehiro, Masayoshi Koike, Hideaki Kato
  • Patent number: 6946370
    Abstract: In a separation layer removing process ?, temperature in a reaction chamber (heat treatment temperature TX) is raised to about 1000° C. and a separation layer A is evaporated through thermal decomposition, to thereby separate about 10 ?m in thickness of protection layer B from a base substrate side (a sapphire substrate 101 comprising a buffer layer 102). Because decomposition temperature of the separation layer A is higher than growth temperature of the protection layer B (about 650° C.) and lower than growth temperature of the semiconductor crystal C (about 1000° C.), the separation layer A vanishes (evaporates) by thermal decomposition, which generates this separation process. Accordingly, a semiconductor crystal having a cross sectional structure shown in FIG. 2B is obtained.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: September 20, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Hiroshi Watanabe
  • Patent number: 6897138
    Abstract: The method of the invention for producing a Group III nitride compound semiconductor, employing an etchable substrate which is produced from a material other than the Group III nitride compound semiconductor, includes stacking one or more layers of the Group III nitride compound semiconductor on one face of the substrate and etching the other face of the substrate while stacking one or more semiconductor layers or after completion of stacking one or more semiconductor layers, to thereby reduce the thickness of most of the substrate. The apparatus of present invention for producing a semiconductor through vapor phase growth, contains a substrate for vapor-phase-growing the semiconductor; a source-supplying system for supplying a source for vapor phase growth of the semiconductor; and an etchant-supplying system, wherein the source-supplying system and the etchant-supplying system are isolated through placement of the substrate.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: May 24, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Hiroshi Watanabe, Masayoshi Koike
  • Publication number: 20050093099
    Abstract: The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations. A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, stripe, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer 31 can be prevented.
    Type: Application
    Filed: November 2, 2004
    Publication date: May 5, 2005
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Yuta Tezen, Toshio Hiramatsu, Seiji Nagai
  • Patent number: 6860943
    Abstract: Disclosed is a method for producing a Group III nitride compound semiconductor including a pit formation step in which a portion of an uppermost layer of a first Group III nitride compound semiconductor layer containing one or more sub-layers, the portion containing lattice defects, is subjected to treatment by use of a solution or vapor which corrodes the portion more easily than it corrodes a portion of the uppermost layer containing no lattice defects, the first Group III nitride compound semiconductor layer not being accompanied by a substrate therefor as a result of removal therefrom, or being accompanied by a substrate such that the semiconductor layer is formed with or without intervention of a buffer layer provided on the substrate; and a lateral growth step of growing a second Group III nitride compound semiconductor layer through vertical and lateral epitaxial overgrowth around nuclei as seeds for crystal growth which are on flat portions of the uppermost layer of the first Group III nitride compoun
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: March 1, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Hiroshi Watanabe
  • Patent number: 6861305
    Abstract: The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations. A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, strip, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer is 31 can be prevented.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: March 1, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Yuta Tezen, Toshio Hiramatsu, Seiji Nagai
  • Patent number: 6855620
    Abstract: A GaN layer 31 is subjected to etching, so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby providing a trench/mesa structure including mesas and trenches whose bottoms sink into the surface of a substrate base 1. Subsequently, a GaN layer 32 is lateral-epitaxially grown with the top surfaces of the mesas and sidewalls of the trenches serving as nuclei, to thereby fill upper portions of the trenches (depressions of the substrate base 1), and then epitaxial growth is effected in the vertical direction. In this case, propagation of threading dislocations contained in the GaN layer 31 can be prevented in the upper portion of the GaN layer 32 that is formed through lateral epitaxial growth.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: February 15, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Seiji Nagai, Yuta Tezen
  • Publication number: 20050032344
    Abstract: A semiconductor laser comprises a sapphire substrate, an AlN buffer layer, Si-doped GaN n-layer, Si-doped Al0.1Ga0.9N n-cladding layer, Si-doped GaN n-guide layer, an active layer having multiple quantum well (MQW) structure in which about 35 ? in thickness of GaN barrier layer 62 and about 35 ? in thickness of Ga0.95In0.05N well layer 61 are laminated alternately, Mg-doped GaN p-guide layer, Mg-doped Al0.25Ga0.75N p-layer, Mg-doped Al0.1Ga0.9N p-cladding layer, and Mg-doped GaN p-contact layer are formed successively thereon. A ridged hole injection part B which contacts to a ridged laser cavity part A is formed to have the same width as the width w of an Ni electrode. Because the p-layer has a larger aluminum composition, etching rate becomes smaller and that can prevent from damaging the p-guide layer in this etching process.
    Type: Application
    Filed: August 25, 2004
    Publication date: February 10, 2005
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Takashi Hatano, Sho Iwayama, Masayoshi Koike
  • Patent number: 6830948
    Abstract: By using a mask 4, a first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, striped-shaped, or grid-like structure, so as to provide a trench/post. Thus, without removing the mask 4 formed on a top surface of the upper layer of the post, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, with a sidewall/sidewalls of the trench serving as a nucleus, to thereby bury the trench and also grow the layer in the vertical direction. The second Group III nitride compound layer 32 does not grow epitaxially on the mask 4. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth and a region having less threading dislocations can be formed in the buried portion of the trench.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: December 14, 2004
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Akira Kojima, Toshio Hiramatsu, Yuta Tezen
  • Publication number: 20040241966
    Abstract: In a separation layer removing process &agr;, temperature in a reaction chamber (heat treatment temperature TX) is raised to about 1000° C. and a separation layer A is evaporated through thermal decomposition, to thereby separate about 10 &mgr;m in thickness of protection layer B from a base substrate side (a sapphire substrate 101 comprising a buffer layer 102). Because decomposition temperature of the separation layer A is higher than growth temperature of the protection layer B (about 650° C.) and lower than growth temperature of the semiconductor crystal C (about 1000° C.), the separation layer A vanishes (evaporates) by thermal decomposition, which generates this separation process. Accordingly, a semiconductor crystal having a cross sectional structure shown in FIG. 2B is obtained.
    Type: Application
    Filed: May 13, 2004
    Publication date: December 2, 2004
    Inventors: Masayoshi Koike, Hiroshi Watanabe
  • Patent number: 6821800
    Abstract: In a method of manufacturing a semiconductor light-emitting device involving the steps of: forming a first semiconductor layer; forming a light-emitting layer of superlattice structure by laminating a barrier layer being made of InY1Ga1-Y1N (Y1≧0) and a quantum well layer being made of InY2Ga1-Y2N (Y2>Y1 and Y2>0) on the first semiconductor layer; and forming a second semiconductor layer on the light-emitting layer, an uppermost barrier layer, which will become an uppermost layer of the light-emitting layer, is made thicker than the other barrier layers. Further, at the time of forming the second semiconductor layer, an upper surface of such uppermost barrier layer is caused to disappear so that the thickness of the uppermost barrier layer becomes substantially equal to those of the other barrier layers.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: November 23, 2004
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Norikatsu Koide, Shinya Asami, Junichi Umezaki, Masayoshi Koike, Shiro Yamasaki, Seiji Nagai
  • Publication number: 20040219702
    Abstract: In the epitaxial growth process in which each growth region D is zoned by a mask 2 formed in grid pattern, because a consumption region C of the Group III nitride compound semiconductor is formed in the central portion of each band of the mask 2 between each adjacent edge portion of the growth region D, Group III or Group V raw material is never unnecessarily supplied to the edge portion of the growth region D. As a result, difference of Group III or Group V rare material supply amount to the edge portion and central portion of the device formation region D is suppressed and the edge portion of the device region may not be convexity.
    Type: Application
    Filed: January 8, 2004
    Publication date: November 4, 2004
    Inventors: Seiji Nagai, Masayoshi Koike, Kazuyoshi Tomita
  • Patent number: 6801559
    Abstract: A semiconductor laser comprises a sapphire substrate, an AlN buffer layer, Si-doped GaN n-layer, Si-doped Al0.1Ga0.9N n-cladding layer, Si-doped GaN n-guide layer, an active layer having multiple quantum well (MQW) structure in which about 35 Å in thickness of GaN barrier layer 62 and about 35 Å in thickness of Ga0.95In0.55N well layer 61 are laminated alternately, Mg-doped GaN p-guide layer, Mg-doped Al0.25Ga0.75N p-layer, Mg-doped Al0.1Ga0.9N p-cladding layer, and Mg-doped GaN p-contact layer are formed successively thereon. A ridged hole injection part B which contacts to a ridged laser cavity part A is formed to have the same width as the width w of an Ni electrode. Because the p-layer has a larger aluminum composition, etching rate becomes smaller and that can prevent from damaging the p-guide layer in this etching process.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: October 5, 2004
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Takashi Hatano, Sho Iwayama, Masayoshi Koike