Abstract: A method of forming a pattern according to the present invention comprising preparing a reduced projection exposure apparatus having a reduced projection ratio 1/m and a wavelength ? (nm) of exposing light and patterning a light shielding element pattern of a reticle mask on a resist film having a thickness tr (nm). The light shielding element pattern has a pattern opening portion having a minimum opening dimension D (nm). A thickness t0 of the light shielding element pattern is set so as to meet a relational equation of m*tr?t0+5*D*D/?. Preferably, the thickness t0 of the light shielding element pattern is set so as to meet a relational equation of m*tr?t0+D*D/?.

Abstract: An AlCu film is formed by simultaneously depositing AlCu within a via hole and on top of an interlayer dielectric film. The surface of the AlCu film is polished using a CMP process, and a TiN antireflection layer is formed thereon. The TiN antireflection layer having a flat surface prevents halation during pattering the interconnections including the AlCu film, thereby preventing ingress of etching solution during a subsequent wet etching process.

Abstract: A contact plug is formed in a contact hole which is formed in an interlayer insulation film and then a barrier metal layer and a main wiring layer, which form a wiring layer in all, are formed on both of the interlayer insulation film and the contact plug. After a surface of the main wiring layer is flattened by means of CMP, an antireflection film is formed on the main wiring layer. After that, a resist pattern is formed on the antireflection film to pattern the wiring layer. Thus, it is possible to pattern the wiring layer finely without influence of unevenness caused by the contact plug located under the wiring layer.

Abstract: In a method of manufacturing a semiconductor device, an insulating film with a concave portion is formed on a semiconductor wafer. A barrier layer is formed on the insulating film to cover a surface of the insulating film such that the barrier layer has a uniform crystal orientation over a whole wafer surface of the semiconductor wafer. A metal film is formed on the barrier layer such that a portion of the metal film fills the concave portion, and a CMP (Chemical Mechanical Polishing) method is performed on the metal film to leave the filling portion of the metal film.

Abstract: A filter rod making machine comprises a plurality of feed wheels (50) for feeding filter elements (fA, fC) at intervals; a conveyor (18) for receiving the filter elements (fA, fC) from the feed wheels (50) and forming an element stream in which the filter elements (fA) and the filter element (fC) are arranged alternately; a wrapping apparatus (62) for forming the element stream into a composite element column (CE) in which the filter elements (fA, fC) are in close contact with each other, and then into a composite element rod (ER) by wrapping the composite element column (CE) in a paper web (W); a cutting apparatus (92) for cutting the composite element rod (ER) into individual filter rods (FR); and a phase change apparatus (112) for adjusting the rotation phase of the feed wheel (50) on the basis of information on the filter rod (FR) cut.

Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved

Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved

Abstract: An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode (9; see FIGS. 31 and 32) of a MISFET (Qs, Qn, Qp) A polysilazan SOG film (57) not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 62, 63).

Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

Abstract: A semiconductor device has a reduced contact resistance between a tungsten film and a polysilicon layer and has a gate electrode prevented from being depleted for a reduced gate resistance. According to a method of fabricating such a semiconductor device, a semiconductor device having a gate electrode of a polymetal gate structure which comprises a three-layer structure having a tungsten (W) film, a tungsten nitride (WN) film, and a polysilicon (PolySi) layer, is manufactured by nitriding the sides of the gate electrode at a nitriding temperature ranging from 700° C. to 950° C. in an ammonia atmosphere after the gate electrode is formed and before side selective oxidization is performed on the gate electrode.

Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

Abstract: The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

Abstract: An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode 9 of a MISFET (Qs, Qn, Qp) A polysilazan SOG film 57 not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 63).

Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

Abstract: An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode 9 of a MISFET (Qs, Qn, Qp). A polysilazan SOG film 57 not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 62, 63).

Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

Abstract: The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.