Patents by Inventor Masayoshi Saito
Masayoshi Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20020182798Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.Type: ApplicationFiled: May 31, 2002Publication date: December 5, 2002Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
-
Patent number: 6479899Abstract: The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.Type: GrantFiled: April 24, 1998Date of Patent: November 12, 2002Assignee: Hitachi, Ltd.Inventors: Takuya Fukuda, Nobuyoshi Kobayashi, Yoshitaka Nakamura, Masayoshi Saito, Shinichi Fukada, Yoshifumi Kawamoto
-
Patent number: 6432769Abstract: The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.Type: GrantFiled: August 22, 2000Date of Patent: August 13, 2002Assignee: Hitachi, Ltd.Inventors: Takuya Fukuda, Nobuyoshi Kobayashi, Yoshitaka Nakamura, Masayoshi Saito, Shinichi Fukada, Yoshifumi Kawamoto
-
Patent number: 6399438Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.Type: GrantFiled: April 9, 2001Date of Patent: June 4, 2002Assignee: Hitachi, Ltd.Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
-
Publication number: 20020048967Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity there of is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.Type: ApplicationFiled: December 13, 2001Publication date: April 25, 2002Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
-
Patent number: 6303478Abstract: A method of fabricating a semiconductor device having, for example, a memory cell array portion and a peripheral circuit portion is disclosed. By such a method, a first interlayer insulating film is formed on a semiconductor substrate, a first connection hole is formed by selectively removing a predetermined portion of the first interlayer insulating film, the sides of the first hole being substantially vertical to the bottom thereof, a first plug is formed by padding the first hole with a metallic film and, subsequently, a second interlayer insulating film is formed on the first insulating film, a second hole is formed by selectively removing a predetermined portion of the second interlayer insulating film, the sides of the second hole being substantially vertical to the bottom thereof, and a second plug aligned to be in direct connection with the first plug is formed by padding the second hole with the metallic film.Type: GrantFiled: October 19, 1999Date of Patent: October 16, 2001Assignee: Hiatchi, Ltd.Inventors: Yoshitaka Nakamura, Nobuyoshi Kobayashi, Takuya Fukuda, Masayoshi Saito
-
Publication number: 20010024870Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.Type: ApplicationFiled: January 31, 2001Publication date: September 27, 2001Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
-
Publication number: 20010023099Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.Type: ApplicationFiled: April 9, 2001Publication date: September 20, 2001Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
-
Patent number: 6235620Abstract: Described is a process for manufacturing a semiconductor integrated circuit device, to expose semiconductor regions over the surface of a semiconductor substrate in self-alignment to wiring lines (including gate electrodes) and element isolating regions when forming connection holes. The process includes a first step of coating a semiconductor substrate with a first conductive film, a first insulating film and a second insulating film sequentially, and patterning these films to form first conductive film patterns. A third insulating film is then formed over the semiconductor substrate, on the side walls of the first conductive film patterns and over the second insulating film, and a fourth insulating film is formed over the third insulating film.Type: GrantFiled: August 24, 1999Date of Patent: May 22, 2001Assignee: Hitachi, Ltd.Inventors: Masayoshi Saito, Makoto Yoshida, Hiroshi Kawakami, Tadashi Umezawa
-
Patent number: 6228791Abstract: The present invention is a solid catalyst component for polymerization of olefins prepared by contacting a magnesium compound, a tetravalent halogen-containing titanium compound, a diester of an aromatic dicarboxylic acid, an aromatic hydrocarbon and an organic aluminum compound containing a hydroxyl group represented by the following general formula (R1CO2)mAl(OH)3-m or aluminum hydroxide. The catalyst for polymerization of olefins comprising said solid catalyst component, an organic aluminum compound represented by the general formula R2pAlQ3-p and an organic silicon compound represented by the general formula R3qSi(OR4)4-q can retard the rate of forming a polymer having a low molecular weight or a low stereoregular polymer which is soluble in a polymerization solvent in slurry polymerization and can obtain a high stereoregular polymer in a high yield, and also can obtain a copolymer having an excellent property in a high yield in the copolymerization of olefins.Type: GrantFiled: July 6, 1999Date of Patent: May 8, 2001Assignee: Toho Titanium Co., Ltd.Inventors: Takuo Kataoka, Masayoshi Saito, Isa Nishiyama
-
Patent number: 6215144Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.Type: GrantFiled: January 25, 1999Date of Patent: April 10, 2001Assignee: Hitachi, Ltd.Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
-
Patent number: 6197702Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.Type: GrantFiled: May 29, 1998Date of Patent: March 6, 2001Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
-
Patent number: 6090903Abstract: A propylene homopolymer having a high stereo-regularity and an excellent processability during sheet or film formation, characterized in that it exhibits a melt flow rate (MFR) of from 0.1 to 20 g/10 min., a xylene-soluble component content of not more than 6% by weight and an isoblock content [IB] of at least 3 mol % as determined by the following equation (1) from Pmmmr, Pmmrr and Pmrrm, which are absorption intensities attributed to isoblock chain in xylene-insoluble component by .sup.13 C-NMR spectrum:[IB]=[Pmmmr]+[Pmmrr]+[Pmrrm] (1)wherein [Pmmmr], [Pmmrr] and [Pmrrm] are the relative intensity ratio (mol %) of Pmmmr, Pmmrr and Pmrrm, respectively, which are absorption intensities attributed to isoblock chain.Type: GrantFiled: December 4, 1997Date of Patent: July 18, 2000Assignee: Toho Titanium Co., Ltd.Inventors: Takuo Kataoka, Masayoshi Saito
-
Patent number: 5986299Abstract: A semiconductor integrated circuit device of the invention is provided with a memory cell array portion and a peripheral circuit portions. In the memory cell array portion, a plurality of plugs which penetrate each of a plurality of interlayer insulating films and the sides of which are almost vertical are directly connected in sequence. In the peripheral circuit portion, a plurality of plugs are mutually connected through contact pads for wiring.Type: GrantFiled: November 3, 1997Date of Patent: November 16, 1999Assignee: Hitachi, Ltd.Inventors: Yoshitaka Nakamura, Nobuyoshi Kobayashi, Takuya Fukuda, Masayoshi Saito
-
Patent number: 5620082Abstract: A changing apparatus comprises first and second rotating disks arranged at the terminal end portion of a first transportation path which extends form a cigarette manufacturing apparatus and transports manufactured double cigarettes, pinch grooves formed individually on parts of the respective peripheral surfaces of the first and second rotating disks, and a push groove formed on the remaining portion of the first rotating disk. As the first and second rotating disks rotate, the pinch grooves accelerate a leading double cigarette on the first transportation path in a manner such that they cyclically face each other to hold the double cigarette between them. The push groove forces out the accelerated double cigarette in the transportation direction of a second transportation path in a filter attachment.Type: GrantFiled: June 29, 1995Date of Patent: April 15, 1997Assignee: Japan Tobacco Inc.Inventor: Masayoshi Saito
-
Patent number: 5298271Abstract: A method for preventing refined edible oils and fats from deteriorating during transportation and/or storage thereof over a prolonged period of time, wherein the refined edible oils and fats are stored and/or transported at all times under an atmosphere rich in nitrogen gas. This nitrogen-enriched atmosphere contains nitrogen in a concentration not lower than 99.5%.Type: GrantFiled: July 30, 1992Date of Patent: March 29, 1994Assignee: Fuji Oil Co., Ltd.Inventors: Shoichi Takashina, Takashi Hazama, Akira Kurooka, Norio Maruguchi, Hiroshi Iwasa, Masayoshi Saito
-
Patent number: 5297014Abstract: A DC power supply apparatus includes a switching transformer having a switching element, a primary current detection circuit, arranged on a primary side of the transformer, for detecting a current flowing in the switching element, a secondary current detection circuit for detecting an output current from a secondary side of the transformer, and a control circuit for controlling the switching element on the basis of outputs from the primary and secondary current detection circuit.Type: GrantFiled: January 3, 1992Date of Patent: March 22, 1994Assignee: Canon Kabushiki KaishaInventors: Masayoshi Saito, Takashi Birumachi
-
Patent number: 5186183Abstract: In an apparatus for detecting micro-holes of a cigarette having a filtered section, cigarettes are successively carried to a support section which is rotated and each of the cigarettes is supported between pads 14a and 14b. The supported cigarette is moved to a pre-pressuring stage in which one end face of the cigarette is closed and a pre-pressure is applied to other end face of the cigarette from a pre-pressure source. Therefore, the cigarette is reached to a measuring stage in which a measuring pressure is applied to the other end face of the cigarette so that air flows through micro-holes of the filter section and a reduced pressure is appeared in the one end of the cigarette. The measuring and reduces pressures are detected by pressure transducers and electrical signals from the transducers are proceed so that dilution value of the cigarette is calculated.Type: GrantFiled: December 7, 1990Date of Patent: February 16, 1993Assignee: Japan Tobacco Inc.Inventors: Mikio Komori, Shuichi Sato, Kazuyu Adachi, Masayoshi Saito
-
Patent number: 4983532Abstract: Microfabrication and large scale integration of a device can be realized by using a planar heterojunction bipolar transistor formed by a process comprising successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction, wherein a collector drawing-out metal layer is formed by the selective CVD method.Type: GrantFiled: December 20, 1988Date of Patent: January 8, 1991Assignee: Hitachi, Ltd.Inventors: Katsuhiko Mitani, Tomonori Tanoue, Chushirou Kusano, Susumu Takahashi, Masayoshi Saito, Hiroshi Miyazaki, Fumio Murai
-
Patent number: 4806335Abstract: A process for producing acicular .alpha.-FeOOH particle powder having a narrow particle size distribution and a rectified shape and being highly dispersed is provided, which process comprises mixing with stirring an aqueous solution of a Fe(II) salt with an aqueous solution of an alkali in an equivalent ratio of alkali to Fe(II) salt of 1.5 or more, oxidizing the mixture with a O.sub.2 -containing gas, heat treating the resulting suspension of iron .alpha.-FeOOH particle powder to 60.degree. to 100.degree. C., further adding an aqueous solution of a FE(II) salt in a proportion of atom to molecule of Fe(II)/.alpha.-FeOOH of 0.5 to 10% and again oxidizing the mixture with a O.sub.2 -containing gas at 35.degree. to 55.degree. C.Type: GrantFiled: November 12, 1987Date of Patent: February 21, 1989Assignee: Chisso CorporationInventors: Masayoshi Saito, Jiro I