Patents by Inventor Masayuki Hiroi
Masayuki Hiroi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11925027Abstract: A semiconductor structure includes a memory array including first and second bit lines and a sense amplifier circuit. The sense amplifier circuit includes a first sense amplifier array containing first active sense amplifier transistors that each have an active region having a first width, where the first active sense amplifier transistors are electrically connected to the first bit lines, and a second sense amplifier array including second active sense amplifier transistors that each have the active region having the first width, where the second active sense amplifier transistors are electrically connected to the second bit lines, and dummy active regions which are electrically inactive located between columns of the second active sense amplifier transistors.Type: GrantFiled: December 27, 2021Date of Patent: March 5, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Takuma Takimoto, Masayuki Hiroi, Hiroyuki Ogawa, Masatoshi Okumura
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Publication number: 20230209832Abstract: A semiconductor structure includes a memory array including first and second bit lines and a sense amplifier circuit. The sense amplifier circuit includes a first sense amplifier array containing first active sense amplifier transistors that each have an active region having a first width, where the first active sense amplifier transistors are electrically connected to the first bit lines, and a second sense amplifier array including second active sense amplifier transistors that each have the active region having the first width, where the second active sense amplifier transistors are electrically connected to the second bit lines, and dummy active regions which are electrically inactive located between columns of the second active sense amplifier transistors.Type: ApplicationFiled: December 27, 2021Publication date: June 29, 2023Inventors: Takuma TAKIMOTO, Masayuki HIROI, Hiroyuki OGAWA, Masatoshi OKUMURA
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Patent number: 11508749Abstract: A semiconductor structure includes a first-conductivity-type well located in a semiconductor substrate, a semiconductor active area region located adjacent to the a first-conductivity-type well, a first transistor including a source region, a drain region, a channel region located between the source region and the drain region, a gate dielectric layer located over the channel region and a gate electrode located over the gate dielectric layer, such that the transistor is located on the semiconductor active area region, and a cutoff gate electrode located over the semiconductor active area region, and between the first transistor and the first-conductivity-type well.Type: GrantFiled: June 15, 2020Date of Patent: November 22, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Takuma Takimoto, Masayuki Hiroi, Akira Inoue
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Publication number: 20210391351Abstract: A semiconductor structure includes a first-conductivity-type well located in a semiconductor substrate, a semiconductor active area region located adjacent to the a first-conductivity-type well, a first transistor including a source region, a drain region, a channel region located between the source region and the drain region, a gate dielectric layer located over the channel region and a gate electrode located over the gate dielectric layer, such that the transistor is located on the semiconductor active area region, and a cutoff gate electrode located over the semiconductor active area region, and between the first transistor and the first-conductivity-type well.Type: ApplicationFiled: June 15, 2020Publication date: December 16, 2021Inventors: Takuma TAKIMOTO, Masayuki HIROI, Akira INOUE
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Patent number: 11081443Abstract: A first vertically alternating sequence of first insulating layers and first spacer material layers and a first-tier retro-stepped dielectric material portion are formed over a substrate. The first spacer material layers are formed as, or are subsequently replaced with, first electrically conductive layers. A second vertically alternating sequence of second insulating layers and second spacer material layers and a second-tier retro-stepped dielectric material portion are formed over the first vertically alternating sequence and the first-tier retro-stepped dielectric material portion. The second spacer material layers are formed as, or are subsequently replaced with, second electrically conductive layers. An opening is formed through the second vertically alternating sequence over the first-tier retro-stepped dielectric material portion, and is filled with a dielectric well structure.Type: GrantFiled: March 24, 2020Date of Patent: August 3, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Yuki Mizutani, Masayuki Hiroi, Fumiaki Toyama
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Publication number: 20200266206Abstract: A three-dimensional semiconductor device includes bit lines formed in the lower-interconnect-level dielectric material layers located over a substrate, bit-line-connection via structures contacting a respective one of the bit lines, pillar-shaped drain regions contacting a respective one of the bit-line-connection via structures, an alternating stack of insulating layers and electrically conductive layers located over the pillar-shaped drain regions, and memory stack structures extending through the alternating stack. A source layer overlies the alternating stack, and is electrically connected to an upper end of each vertical semiconductor channel within a subset of the vertical semiconductor channels. Vertical bit line interconnections structures extending through the levels of the alternating stack may be eliminated by forming the bit lines underneath the alternating stack, and the footprint of the layout of the three-dimensional memory device may be reduced.Type: ApplicationFiled: February 18, 2019Publication date: August 20, 2020Inventors: Noritaka Fukuo, Masayuki Hiroi
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Patent number: 10734400Abstract: A three-dimensional semiconductor device includes bit lines formed in the lower-interconnect-level dielectric material layers located over a substrate, bit-line-connection via structures contacting a respective one of the bit lines, pillar-shaped drain regions contacting a respective one of the bit-line-connection via structures, an alternating stack of insulating layers and electrically conductive layers located over the pillar-shaped drain regions, and memory stack structures extending through the alternating stack. A source layer overlies the alternating stack, and is electrically connected to an upper end of each vertical semiconductor channel within a subset of the vertical semiconductor channels. Vertical bit line interconnections structures extending through the levels of the alternating stack may be eliminated by forming the bit lines underneath the alternating stack, and the footprint of the layout of the three-dimensional memory device may be reduced.Type: GrantFiled: February 18, 2019Date of Patent: August 4, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Noritaka Fukuo, Masayuki Hiroi
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Patent number: 10263066Abstract: The present invention is directed to a semiconductor integrated circuit device that basically has a non-memory array area, a memory array area, and memory capacitors formed across lower embedded metal interconnection layers including a low-dielectric constant interlayer insulating film in the memory array area. In addition, a memory-periphery metal seal ring is provided in the lower embedded metal interconnection layers having at least the low-dielectric constant interlayer insulating film so as to surround the memory array area.Type: GrantFiled: March 28, 2013Date of Patent: April 16, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masayuki Hiroi, Takashi Sakoh
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Patent number: 9613975Abstract: A structure is formed on a substrate, which includes a stack of alternating layers comprising insulating layers and electrically conductive layers and a plurality of memory stack structures extending through the stack. At least one bridge line structure is formed on top surfaces of a respective subset of the plurality of memory stack structures to provide local lateral electrical connection. At least one dielectric material layer is formed over the at least one bridge line structure and the plurality of memory stack structures. A plurality contact via structures is formed through the dielectric material layer. The plurality of contact via structures includes at least one first contact via structure contacting a top surface of a respective bridge line structure, and second contact via structures contacting a top surface of a respective memory stack structure.Type: GrantFiled: March 31, 2015Date of Patent: April 4, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Chenche Huang, Chun-Ming Wang, Yuki Mizutani, Hiroaki Koketsu, Masayuki Hiroi, Masaaki Higashitani
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Publication number: 20160293621Abstract: A structure is formed on a substrate, which includes a stack of alternating layers comprising insulating layers and electrically conductive layers and a plurality of memory stack structures extending through the stack. At least one bridge line structure is formed on top surfaces of a respective subset of the plurality of memory stack structures to provide local lateral electrical connection. At least one dielectric material layer is formed over the at least one bridge line structure and the plurality of memory stack structures. A plurality contact via structures is formed through the dielectric material layer. The plurality of contact via structures includes at least one first contact via structure contacting a top surface of a respective bridge line structure, and second contact via structures contacting a top surface of a respective memory stack structure.Type: ApplicationFiled: March 31, 2015Publication date: October 6, 2016Inventors: Chenche Huang, Chun-Ming Wang, Yuki Mizutani, Hiroaki Koketsu, Masayuki Hiroi, Masaaki Higashitani
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Patent number: 9449929Abstract: In a semiconductor device including a seal ring area containing multiple seal rings are coupled to each other at equal intervals via bridge patterns, improper local relocation of bridge patterns may reduce the reliability of the semiconductor device. A semiconductor device has a first group containing a predetermined number of the bridge patterns spaced at a first interval and a second group containing a predetermined number of the bridge patterns spaced at the first interval, the second group being located at a second interval from the first group. The second interval is larger than the first interval.Type: GrantFiled: July 6, 2015Date of Patent: September 20, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takumi Saito, Masayuki Hiroi
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Publication number: 20150311166Abstract: In a semiconductor device including a seal ring area containing multiple seal rings are coupled to each other at equal intervals via bridge patterns, improper local relocation of bridge patterns may reduce the reliability of the semiconductor device. A semiconductor device has a first group containing a predetermined number of the bridge patterns spaced at a first interval and a second group containing a predetermined number of the bridge patterns spaced at the first interval, the second group being located at a second interval from the first group. The second interval is larger than the first interval.Type: ApplicationFiled: July 6, 2015Publication date: October 29, 2015Inventors: Takumi SAITO, Masayuki HIROI
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Patent number: 9111063Abstract: In a semiconductor device including a seal ring area containing multiple seal rings are coupled to each other at equal intervals via bridge patterns, improper local relocation of bridge patterns may reduce the reliability of the semiconductor device. A semiconductor device has a first group containing a predetermined number of the bridge patterns spaced at a first interval and a second group containing a predetermined number of the bridge patterns spaced at the first interval, the second group being located at a second interval from the first group. The second interval is larger than the first interval.Type: GrantFiled: March 11, 2014Date of Patent: August 18, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takumi Saito, Masayuki Hiroi
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Publication number: 20140264901Abstract: In a semiconductor device including a seal ring area containing multiple seal rings are coupled to each other at equal intervals via bridge patterns, improper local relocation of bridge patterns may reduce the reliability of the semiconductor device. A semiconductor device has a first group containing a predetermined number of the bridge patterns spaced at a first interval and a second group containing a predetermined number of the bridge patterns spaced at the first interval, the second group being located at a second interval from the first group. The second interval is larger than the first interval.Type: ApplicationFiled: March 11, 2014Publication date: September 18, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takumi SAITO, Masayuki Hiroi
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Patent number: 8663882Abstract: To provide an electrophotographic photoreceptor excellent in electric characteristics and various characteristics, capable of forming a uniform photosensitive layer and excellent in repetitive characteristics, an image forming apparatus using it and an electrophotgraphic cartridge. A lamination type electrophotographic photoreceptor comprising an electroconductive substrate and a photosensitive layer formed thereon, characterized in that the photosensitive layer contains a compound represented by the following formula (1), the ratio of the weight of the compound represented by the formula (1) to the weight content of all binder resins contained in the photosensitive layer is from 0.15 to 0.Type: GrantFiled: September 28, 2006Date of Patent: March 4, 2014Assignee: Mitsubishi Chemical CorporationInventors: Teruyuki Mitsumori, Masayuki Hiroi, Hiroaki Takamura
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Patent number: 8609309Abstract: To provide an electrophotographic photoreceptor having a high sensitivity, a good balance of various electric properties such as chargeability and residual potential, a good stability of the coating solution, and an excellent light resistance. An electrophotographic photoreceptor comprising an electroconductive support having thereon a photosensitive layer, wherein the photosensitive layer contains a compound represented by the following formula (1): (wherein R1 represents a group having a chiral center, R2 represents a hydrogen atom, an alkyl group which may have a substituent, or an aryl group which may have a substituent, R3 and R4 each independently represents an alkylene group which may have a substituent, or an arylene group which may have a substituent, and R5, R6, R7 and R8 each independently represents an alkyl group which may have a substituent, or an aryl group which may have a substituent, and at least one member of R5 to R8 is an aryl group having a substituent).Type: GrantFiled: August 16, 2010Date of Patent: December 17, 2013Assignee: Mitsubishi Chemical CorporationInventors: Yuka Nagao, Teruyuki Mitsumori, Masayuki Hiroi
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Patent number: 8598044Abstract: An intermediate film 222 in a three-layered resist film 225 is formed by the chemical vapor deposition process at a temperature not higher than 300° C., using Si(OR1)(OR2)(OR3)(OR4), where each of R1, R2, R3 and R4 independently represents a carbon-containing group or a hydrogen atom, excluding the case where all of R1 to R4 are hydrogen atoms.Type: GrantFiled: June 21, 2005Date of Patent: December 3, 2013Assignee: Renesas Electronics CorporationInventors: Tatsuya Usami, Sadayuki Ohnishi, Masayuki Hiroi, Akira Matsumoto
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Publication number: 20130285203Abstract: The present invention is directed to a semiconductor integrated circuit device that basically has a non-memory array area, a memory array area, and memory capacitors formed across lower embedded metal interconnection layers including a low-dielectric constant interlayer insulating film in the memory array area. In addition, a memory-periphery metal seal ring is provided in the lower embedded metal interconnection layers having at least the low-dielectric constant interlayer insulating film so as to surround the memory array area.Type: ApplicationFiled: March 28, 2013Publication date: October 31, 2013Applicant: Renesas Electronics CorporationInventors: Masayuki HIROI, Takashi SAKOH
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Patent number: 8329584Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: GrantFiled: June 2, 2011Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
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Patent number: 8288066Abstract: To provide an electrophotographic photoreceptor having a high sensitivity, a good balance of various electric properties such as chargeability and residual potential, a good stability of the coating solution, and an excellent light resistance. An electrophotographic photoreceptor comprising an electroconductive support having thereon a photosensitive layer, wherein the photosensitive layer contains a compound represented by the following formula (1): (wherein R1 represents a group having a chiral center, R2 represents a hydrogen atom, an alkyl group which may have a substituent, or an aryl group which may have a substituent, R3 and R4 each independently represents an alkylene group which may have a substituent, or an arylene group which may have a substituent, and R5, R6, R7 and R8 each independently represents an alkyl group which may have a substituent, or an aryl group which may have a substituent, and at least one member of R5 to R8 is an aryl group having a substituent).Type: GrantFiled: January 5, 2006Date of Patent: October 16, 2012Assignee: Mitsubishi Chemical CorporationInventors: Yuka Nagao, Teruyuki Mitsumori, Masayuki Hiroi