Abstract: A fully-differential amplifier able to operate at a low power supply voltage and provided with a common-mode signal suppression function is disclosed. This fully-differential amplifier is provided with a first fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the input side by a feedforward means and a second fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the output side by a feedback means, the output of the first fully-differential amplifier being connected to the input of the second fully-differential amplifier.

Abstract: A resolver use angle detection IC subjected to a phase lock operation so as to follow not an angle ?(t) for detection, but a phase angle ?ot±?(t) having an offset of a frequency ?ot in the phase lock units. For this reason, when the excitation frequency ?ot is set sufficiently high with respect to the frequency of the angle ?(t), the phase angle ?ot±? to be followed in the phase lock units will not become zero. For this reason, an angle having a high precision can be found in real time regardless of the configuration not including the conventional apparatus in which the configuration is complex and the power consumption is large like a bipolar VCO and an up/down type counter.

Abstract: A resolver use angle detection IC subjected to a phase lock operation so as to follow not an angle ?(t) for detection, but a phase angle ?ot±?(t) having an offset of a frequency ?ot in the phase lock units. For this reason, when the excitation frequency ?ot is set sufficiently high with respect to the frequency of the angle ?(t), the phase angle ?ot±? to be followed in the phase lock units will not become zero. For this reason, an angle having a high precision can be found in real time regardless of the configuration not including the conventional apparatus in which the configuration is complex and the power consumption is large like a bipolar VCO and an up/down type counter.

Abstract: A sine wave generation circuit for generating a high precision pseudo sine wave without increasing the circuit size including a pulse generation circuit for generating a plurality of pulse signals using an input clock signal as reference and a voltage output circuit for stepwisely changing the voltage level of the output on the basis of a plurality of pulse signals. The voltage output circuit generates a plurality of different coefficients in response to a combination of bit information in a plurality of pulse signals and changes the output of the voltage output circuit in response to a coefficient series obtained when further combining the plurality of generated coefficients, and odd number generation circuits each generating odd number values of ternary-values or more having positive side coefficients and negative side coefficients symmetric about a center coefficient are provided in a plurality of coefficient generation circuits provided in the voltage output circuit.

Abstract: A phase-locked circuit comprises a complex signal processor and a feedback portion wherein the complex signal processor: receives as an input a first complex signal composed of a real part component and an imaginary part component; generates a second complex signal composed of a first signal component and a second signal component and having a second frequency in accordance with a feedback control signal input from the feedback portion; and generates a signal in accordance with a declination of a third complex signal obtained by multiplying the first complex signal with the second complex signal and outputs to the feedback portion. The feedback portion generates the feedback control signal in accordance with a signal input from the complex signal processor, so that the declination converges to a constant value; and the complex signal processor synchronizes a phase of the second complex signal with the first complex signal and outputs.

Abstract: A sine wave multiplication circuit multiplies an analog input signal by n (n is an integer equal to or greater than 2) weighting coefficients each having a unique value. The polarity of the analog input signal multiplied by one of the n weighting coefficients is changed over. Further, changeover among the n weighting coefficients and of the polarity is performed after every sampling period equal to ½k (k is an integer, and 2k is equal to or greater than 6 but equal to or smaller than 4n) of one period of the sine wave signal by which the analog input signal is multiplied. As a result, a staircase waveform having 2n positive and negative stairs is generated while unnecessary harmonic wave components in the proximity of the sine wave signal by which the analog input signal is multiplied can be reduced.

Abstract: A bias circuit according to the present invention includes a monitoring circuit having a second FET and a resistance connected to a drain of the second FET for monitoring a drain current of a first FET to be supplied with a gate bias; a differential circuit including a third FET having a gate supplied with a reference voltage, a fourth FET having a gate connected to the drain of the second FET, sources of the third FET and the fourth FET being connected to a common point, and resistances connected to drains of the third FET and the fourth FET, respectively; and a fifth FET having a drain connected to the common source of the third FET and the fourth FET; wherein a drain voltage of the third FET is fed back to gates of the first FET and the second FET, and a drain voltage of the fourth FET is fed back to a gate of the fifth FET.

Abstract: A sine wave generation circuit for generating a high precision pseudo sine wave without increasing the circuit size including a pulse generation circuit for generating a plurality of pulse signals using an input clock signal as reference and a voltage output circuit for stepwisely changing the voltage level of the output on the basis of a plurality of pulse signals. The voltage output circuit generates a plurality of different coefficients in response to a combination of bit information in a plurality of pulse signals and changes the output of the voltage output circuit in response to a coefficient series obtained when further combining the plurality of generated coefficients, and odd number generation circuits each generating odd number values of ternary-values or more having positive side coefficients and negative side coefficients symmetric about a center coefficient are provided in a plurality of coefficient generation circuits provided in the voltage output circuit.

Abstract: An oscillator having a modulation function capable of controlling a frequency by adding a signal to a control signal and a PLL circuit using the same, wherein the oscillator forms a ring comprised of a plurality of cascade connected delay stages controlled in delay value by an inverter or a buffer and a control signal and forming a closed loop by an inverted phase and comprises a modulation function modulating an oscillation frequency by adding a modulation signal to the control signal in a part of the plurality of delay stages.

Abstract: An oscillator having a modulation function capable of controlling a frequency by adding a signal to a control signal and a PLL circuit using the same, wherein the oscillator forms a ring comprised of a plurality of cascade connected delay stages controlled in delay value by an inverter or a buffer and a control signal and forming a closed loop by an inverted phase and comprises a modulation function modulating an oscillation frequency by adding a modulation signal to the control signal in a part of the plurality of delay stages.

Abstract: A nonlinearity compensation circuit is disclosed which includes an inverse hyperbolic function generation circuit for converting differential currents corresponding to input signals in+ and in− into differential voltages which increase in proportion to an inverse hyperbolic function, an offset provision circuit for providing an offset corresponding to control signals c+ and c− to the differential voltages outputted from the inverse hyperbolic function generation circuit and a hyperbolic function generation circuit for converting the differential voltages to which the offset has been provided by the offset provision circuit into signals which increase in proportion to a hyperbolic function and outputting the resulting signals as output signals out+ and out−. Consequently, compensation for the nonlinearity such as second order distortion can be performed for the read signal from a recording medium.

Abstract: A nonlinearity compensation circuit is disclosed which includes an inverse hyperbolic function generation circuit for converting differential currents corresponding to input signals in+ and in− into differential voltages which increase in proportion to an inverse hyperbolic function, an offset provision circuit for providing an offset corresponding to control signals c+ and c− to the differential voltages outputted from the inverse hyperbolic function generation circuit and a hyperbolic function generation circuit for converting the differential voltages to which the offset has been provided by the offset provision circuit into signals which increase in proportion to a hyperbolic function and outputting the resulting signals as output signals out+ and out−. Consequently, compensation for the nonlinearity such as second order distortion can be performed for the read signal from a recording medium.

Abstract: A bias circuit according to the present invention includes a monitoring circuit having a second FET and a resistance connected to a drain of the second FET for monitoring a drain current of a first FET to be supplied with a gate bias; a differential circuit including a third FET having a gate supplied with a reference voltage, a fourth FET having a gate connected to the drain of the second FET, sources of the third FET and the fourth FET being connected to a common point, and resistances connected to drains of the third FET and the fourth FET, respectively; and a fifth FET having a drain connected to the common source of the third FET and the fourth FET; wherein a drain voltage of the third FET is fed back to gates of the first FET and the second FET, and a drain voltage of the fourth FET is fed back to a gate of the fifth FET.

Abstract: A liquid crystal display drive circuit capable of reducing deviation between channels and realizing a liquid crystal display of a high image quality without requiring an adjustment step on a manufacturing line.

Abstract: A liquid crystal display device and a data line drive circuit of the same capable of individually reducing offsets between a video signal input and outputs, reducing a difference of offsets among outputs, and accordingly obtaining a good image quality, provided with a plurality of output blocks provided with sample-and-hold circuits connected in series for sampling the input video signal and holding the sampled data for a constant period; a drive circuit for outputting the held data of the sample-and-hold circuit as a signal of a predetermined level; and an output level adjustment circuit for comparing voltages V1 and V2 set in the switching period of the horizontal synchronization signal in the input video signal and an output signal voltage of the drive circuit and adjusting the level of the output signal of the drive circuit to a constant level.

Abstract: An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1 Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.

Abstract: A voltage controlled oscillator which causes little interference to and receives little interference from other circuits via a parasitic capacitance of an integrated capacitor, has a good control linearity, and is capable of being used over a wide range of frequency including ultra high frequencies, constituting a ring oscillator by being provided with three or more logic buffer circuits having differential input and output terminals cascade connected at the differential inputs and outputs and making the n-th differential output a negative feedback to the terminal of the 1st differential input. Each of the logic buffer circuits comprises a differential transistor pair comprised of first and second transistors, first and second diode array each comprising at least one diode, first and second integrated capacitors, and a current source for frequency control. The sum of emitter currents of the pair of the differential transistors is set by the current source for frequency control.

Abstract: By providing differential resistors in common emitters of pairs of differential transistor and differentially taking out signals from collectors, a circuit excellent in low noise property and linearity was obtained. Further, a ring type voltage controlled oscillation circuit is provided comprising n number of stages of variable delay circuits, a control signal generation circuit weighting n+1 outputs taken out of the voltage controlled oscillation circuit by a phase control signal voltage and controlling the phase, and a phase locked loop means for locking the phase by comparing the output of the voltage controlled oscillation circuit and an external pixel clock.

Abstract: A phase adjustment circuit includes a ring oscillator which is phase locked to an external pixel clock by a phase locked loop. The ring oscillator is formed of n number of stages of variable delay circuits providing n+1 outputs of substantially equal phase differences. A control signal generation circuit is responsive to a phase control signal to generate n+1 weighting coefficients for weighting the n+1 outputs from the ring oscillator in a weighting circuit which produces a phase adjusted output signal.

Abstract: A differential amplifier circuit comprises a first differential transistor circuit, a grounded base transistor circuit and a second differential transistor circuit. A pair of transistors of the second differential transistor each produces a current based on an emitter voltage of each of a pair of transistors of the grounded base transistor circuit for cancelling non-linear components of transistors of the first differential transistor circuit. The currents produced by the second differential transistor circuit are each cross-added to an alternating current component of each of the first differential transistor circuit at a collector of each of the pair of transistors of the grounded base transistor circuit. Non-linear components of the first differential transistor circuit are thus cancelled out.