Abstract: A gain control circuit, which has particular utility in a compressor or expander of a noise reduction circuit, is comprised of first and second detectors for detecting the output signal from a variable gain amplifier and providing respective detector outputs for charging first and second capacitors, respectively. Such first and second capacitors have discharge paths in which first and second resistors are respectively interposed, and the charge on the first capacitor is employed as a control signal for determining the gain of the variable gain amplifier. Further, the first resistor is connected between the first and second capacitors so that the discharge current through the first resistor is dependent on the difference between the charge voltages on the first and second capacitors, whereby a relatively long recovery time can be obtained without adversely affecting the attack time even when the input signal to the variable gain amplifier is of low level.

Abstract: An electrically variable impedance circuit in which a voltage-current converter circuit is provided to produce a current having a magnitude corresponding to an instantaneous input signal potential applied to an input terminal and a current variation of the voltage-current converter circuit is fed back to the input terminal, the current variation being controlled by a control signal to vary the circuit impedance seen from the input terminal. In order to expand the range of linearity in impedance, the voltage-current converter is so arranged that the varying component of its output current is linearly proportional to the instantaneous input signal potential, and a current converter circuit is provided which linearly converts the output current of the voltage-current converter circuit and whose output is coupled to the input terminal.

Abstract: A switching circuit having a current source connected to first, second and third lines in order to supply first and second current signals whose total amount remains constant to the first and second current lines, respectively. The current source further supplies a constant bias I.sub.B to the third line. First and second diode pairs are respectively connected in parallel in opposite directions between the first and third signal current lines, and between the second and third signal lines, respectively. First and second transistors are connected to the three signal current lines, respectively, with the base voltages of these transistors kept constant at the same voltage level. Accordingly, current passing through the first and second diode pairs change flow direction in accordance with the incremental variations of current flowing in the first and second lines.

Abstract: A bias circuit comprises first and second cascade-connected transistors of the same conductivity type; series-connected diode means adapted to be forward biased by part of a drive current toward the first and second transistors; and means for applying a voltage across a series circuit of the diode means between the bases of the first and second transistors, emitter voltages of the first and second transistors being applied to a next stage class B push-pull circuit.

Abstract: An RMS circuit comprising a logarithmic amplifying circuit, a fullwave rectifying circuit for subjecting an output from the logarithmic amplifying circuit to fullwave rectification, and a smoothing circuit for smoothing an output signal from the fullwave rectifying circuit, wherein the logarithmic amplifying circuit is provided with an operational amplifier whose noninverting input terminal is grounded and whose inverting input terminal is connected to a signal source; a first npn transistor whose collector is connected to the inverting input terminal of the operational amplifier and whose base is grounded; a first diode whose anode is connected to the emitter of the first npn transistor and whose cathode is connected to the output terminal of the operational amplifier; a second diode whose anode is connected to the output terminal of the operational amplifier; and a third diode whose anode is connected to the cathode of the second diode and whose cathode is connected to the noninverting input terminal of the

Abstract: The collector of an NPN transistor is connected to the inverting terminal of an operational amplifier to cause a collector current of the NPN transistor to be inverted by the operational amplifier. The combination circuit of the NPN transistor and operational amplifier equivalently works as a PNP transistor.

Abstract: A voltage controlled variable gain circuit comprising: first, second, third and fourth same polarity transistors for dividing the output current of a first operational amplifier by dc gain control voltage and being connected with the output terminal of the first operational amplifier to which an input signal is applied; means for driving in inverse phase the respective pairs of a first and third transistors, and a second and fourth transistors; a first feedback circuit including a second operational amplifier with an inverting input terminal connected with the output terminal of the first transistor, a first resistor element and a first PN junction element connected in series between the input and output terminals of the second operational amplifier, and a second resistor element and a second PN junction element connected in series between the output of the second operational amplifier and the input terminal of the first operational amplifier, so as to negatively feedback the output current of the first trans