Patents by Inventor Masayuki Takeda

Masayuki Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240140760
    Abstract: To provide a drive device for a self-propelled elevator which is capable of moving a car in a vertical direction and a horizontal direction with a simple configuration. The drive device for a self-propelled elevator includes: a rotating body which is rotatably coupled to a back face of a cab; and wheels which are provided on the rotating body so as to sandwich guide surfaces of a rail on a back face side of the cab, which generate, by friction between the wheels and the rail, a force that moves the cab in a vertical direction when a longitudinal direction of the rail is the vertical direction, and which generate, by a friction force between the wheels and the rail, a force that moves the cab in a horizontal direction when the longitudinal direction of the rail is the horizontal direction.
    Type: Application
    Filed: March 8, 2021
    Publication date: May 2, 2024
    Applicants: Mitsubishi Electric Corporation, Tokyo Institute of Technology
    Inventors: Yusuke SUGAHARA, Yukio TAKEDA, Takahiro ISHII, Takeshi MATSUMOTO, Masayuki KAKIO
  • Publication number: 20240091775
    Abstract: One object of the present invention is to provide a method or apparatus for purifying target particles from high-concentration particles in a short time. The above problem can be solved by a method for purifying target particles, characterized in that the method comprises a step of sorting the target particles from a high concentration of non-target particles, wherein the sorting step is repeated for three times or more.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Applicant: ON-CHIP BIOTECHNOLOGIES CO., LTD.
    Inventors: Kazuo TAKEDA, Masayuki ISHIGE, Yuu FUJIMURA, Takahide INO, Yuji MORISHITA, Kosuke OSAWA, Soichiro TSUDA
  • Patent number: 11936490
    Abstract: Upon receiving a copy of upstream communication from a first switch, a second switch specifies an NF apparatus serving as a transmission source of the upstream communication, based on apparatus information indicating a MAC address of each apparatus and a transmission source MAC address contained in the copy of the upstream communication. The second switch refers to the apparatus information, and MAC address information indicating, for each port of the switch, a MAC address of an apparatus connected via the port, thereby specifying a port of the second switch connected to the NF apparatus, and a MAC address of the transmission source via the port. The second switch stores session information in which information on the specified port and MAC address is associated with header information set for the copy of the upstream communication. Upon receiving downstream communication, the second switch transfers the downstream communication to the NF apparatus.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: March 19, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yuki Takei, Masayuki Nishiki, Tomonori Takeda
  • Publication number: 20240060496
    Abstract: A vacuum pump and a control device, on a pump side, performs heater control of a pipe to suppress precipitation of a deposit from a process gas and cooling control of a deposit trap to remove the deposit, and perform heater control and cooling control the process gas situation. A temperature sensor is disposed on an outer periphery or an inner periphery of an introduction pipe 3H, outputs temperature information a control device. Temperature information from the inside of a deposit trap is also sent to control device. The control device, performs ON/OFF control a heater such that a temperature of the introduction pipe 3H has a predetermined temperature value, based on the input temperature information 31. The control device, performs opening/closing control on a valve such that an internal temperature of the deposit trap has a predetermined cooling temperature value, based on the input temperature information.
    Type: Application
    Filed: December 21, 2021
    Publication date: February 22, 2024
    Inventors: Shinichi Yoshino, Masayuki Takeda, Naoki Miyasaka
  • Publication number: 20190002988
    Abstract: The present invention relates to a RET fusion gene such as a CCDC6-RET fusion gene as a biomarker to monitor the activity of the compound 3-Z-[1-(4-(N-((4-methyl-piperazin-1-yl)-methylcarbonyl)-N-methyl-amino)-anilino)-1-phenyl-methylene]-6-methoxycarbonyl-2-indolinone or a pharmaceutically acceptable salt thereof, and especially its monoethanesulphonate salt form, when used alone or optionally in combination with further pharmaceutically active ingredients and/or further treatments. The present invention also relates to specific uses of said specific compound in the treatment of cancers.
    Type: Application
    Filed: December 5, 2016
    Publication date: January 3, 2019
    Inventors: Hidetoshi HAYASHI, Kazuhiko NAKAGAWA, Kazuto NISHIO, Kunio OKAMOTO, Kazuko SAKAI, Toshio SHIMIZU, Masayuki TAKEDA, Kaoru TANAKA
  • Patent number: 9608083
    Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: March 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
  • Patent number: 9324808
    Abstract: A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode.
    Type: Grant
    Filed: May 25, 2013
    Date of Patent: April 26, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Norikazu Nakamura, Shirou Ozaki, Masayuki Takeda, Keiji Watanabe
  • Patent number: 9165851
    Abstract: A semiconductor device includes a compound semiconductor multilayer structure, a fluorine-containing barrier film that covers a surface of the compound semiconductor multilayer structure, and a gate electrode that is arranged over the compound semiconductor multilayer structure with the fluorine-containing barrier film placed the gate and the compound semiconductor multilayer structure.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: October 20, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Masayuki Takeda
  • Publication number: 20150279956
    Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.
    Type: Application
    Filed: June 9, 2015
    Publication date: October 1, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
  • Patent number: 8866157
    Abstract: A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 21, 2014
    Assignee: Fujitsu Limited
    Inventors: Norikazu Nakamura, Shirou Ozaki, Masayuki Takeda, Toyoo Miyajima, Toshihiro Ohki, Masahito Kanamura, Kenji Imanishi, Toshihide Kikkawa, Keiji Watanabe
  • Patent number: 8815017
    Abstract: A method of manufacturing a semiconductor device includes: holding a semiconductor substrate with a surface inclined with respect to the vertical direction and the horizontal direction; and immersing the semiconductor substrate in a cleaning solution including an acid.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: August 26, 2014
    Assignee: Fujitsu Limited
    Inventors: Shirou Ozaki, Masayuki Takeda, Norikazu Nakamura, Junichi Kon
  • Patent number: 8637409
    Abstract: An etching method includes: applying a radiation to an etching aqueous solution; and etching a material to be etched by using the etching aqueous solution irradiated with the radiation.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: January 28, 2014
    Assignee: Fujitsu Limited
    Inventors: Shirou Ozaki, Masayuki Takeda
  • Publication number: 20130306102
    Abstract: A method of manufacturing a semiconductor device includes: holding a semiconductor substrate with a surface inclined with respect to the vertical direction and the horizontal direction; and immersing the semiconductor substrate in a cleaning solution including an acid.
    Type: Application
    Filed: July 26, 2013
    Publication date: November 21, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Masayuki TAKEDA, Norikazu NAKAMURA, Junichi KON
  • Publication number: 20130256693
    Abstract: A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode.
    Type: Application
    Filed: May 25, 2013
    Publication date: October 3, 2013
    Applicant: Fujitsu Limited
    Inventors: Norikazu NAKAMURA, Shirou OZAKI, Masayuki TAKEDA, Keiji WATANABE
  • Publication number: 20130256690
    Abstract: A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component.
    Type: Application
    Filed: May 23, 2013
    Publication date: October 3, 2013
    Inventors: NORIKAZU NAKAMURA, SHIROU OZAKI, MASAYUKI TAKEDA, TOYOO MIYAJIMA, TOSHIHIRO OHKI, MASAHITO KANAMURA, KENJI IMANISHI, TOSHIHIDE KIKKAWA, KEIJI WATANABE
  • Patent number: 8487384
    Abstract: A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: July 16, 2013
    Assignee: Fujitsu Limited
    Inventors: Norikazu Nakamura, Shirou Ozaki, Masayuki Takeda, Keiji Watanabe
  • Publication number: 20130069175
    Abstract: A semiconductor device includes a compound semiconductor multilayer structure, a fluorine-containing barrier film that covers a surface of the compound semiconductor multilayer structure, and a gate electrode that is arranged over the compound semiconductor multilayer structure with the fluorine-containing barrier film placed the gate and the compound semiconductor multilayer structure.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 21, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Masayuki Takeda
  • Publication number: 20120238104
    Abstract: An etching method includes: applying a radiation to an etching aqueous solution; and etching a material to be etched by using the etching aqueous solution irradiated with the radiation.
    Type: Application
    Filed: February 17, 2012
    Publication date: September 20, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Masayuki Takeda
  • Publication number: 20120220105
    Abstract: A method of manufacturing a semiconductor device includes: holding a semiconductor substrate with a surface inclined with respect to the vertical direction and the horizontal direction; and immersing the semiconductor substrate in a cleaning solution including an acid.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 30, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Masayuki Takeda, Norikazu Nakamura, Junichi Kon
  • Publication number: 20120205663
    Abstract: A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 16, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Norikazu NAKAMURA, Shirou OZAKI, Masayuki TAKEDA, Keiji WATANABE