Patents by Inventor Masayuki Terai

Masayuki Terai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9812501
    Abstract: A variable resistance memory device includes a plurality of first conductive layer pattern, a plurality of second conductive layer patterns over the first conductive layer patterns, and a plurality of lower cell structures including a switching element and a variable resistance element, the lower cell structures being formed at intersections at which the first conductive layer patterns and the second conductive layer patterns overlap each other. The first conductive layer patterns, the second conductive layer patterns and the lower cell structures serves as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Woo Lee, Youn-Seon Kang, Seung-Jae Jung, Hyun-Su Ju, Masayuki Terai
  • Publication number: 20170294483
    Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Inventors: Masayuki TERAI, Gwan-hyeob KOH, Dae-hwan KANG
  • Publication number: 20170243918
    Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.
    Type: Application
    Filed: September 6, 2016
    Publication date: August 24, 2017
    Inventors: Masayuki TERAI, Gwan-hyeob KOH, Dae-hwan KANG
  • Patent number: 9741764
    Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: August 22, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Masayuki Terai, Gwan-hyeob Koh, Dae-hwan Kang
  • Publication number: 20170237000
    Abstract: A variable resistance memory device and a method of manufacturing the same, the device including first conductive lines disposed in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, and the first and second directions being parallel to a top surface of the substrate; second conductive lines disposed in the second direction over the first conductive lines, each of the second conductive lines extending in the first direction; a memory unit between the first and second conductive lines, the memory unit being in each area overlapping the first and second conductive lines in a third direction substantially perpendicular to the top surface of the substrate, and the memory unit including a variable resistance pattern; and an insulation layer structure between the first and second conductive lines, the insulation layer structure covering the memory unit and including an air gap in at least a portion of an area overlapping neither the fir
    Type: Application
    Filed: November 9, 2016
    Publication date: August 17, 2017
    Inventors: Masayuki TERAI, Dae-Hwan KANG, Gwan-Hyeob KOH
  • Publication number: 20170117328
    Abstract: A semiconductor device includes: a first memory cell, a bit line and a second memory cell. The first memory cell has a first stack structure including a first memory layer between a first heater electrode and a first ovonic threshold switching device. The bit line is on the first memory cell. The second memory cell is on the bit line, and has a second stack structure including a second memory layer between a second ovonic threshold switching device and a second heater electrode. The first and second stack structures are symmetrical with respect to the bit line.
    Type: Application
    Filed: October 26, 2016
    Publication date: April 27, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Masayuki TERAI
  • Publication number: 20170117327
    Abstract: A semiconductor device includes a first word line and a second word line extending abreast of each other in a first direction. A bit line extends between the first word line and the second word line in a second direction intersecting the first direction. A lower electrode is formed on one surface of the first word line. An ovonic threshold switch (OTS) is formed on the lower electrode. An intermediate electrode is formed on the OTS. A phase change memory (PCM) is formed on the intermediate electrode, and an upper electrode is formed between the first PCM and a surface of the bit line. The width of the first upper electrode in the second direction is narrower than the width of the first intermediate electrode in the second direction.
    Type: Application
    Filed: June 21, 2016
    Publication date: April 27, 2017
    Inventor: MASAYUKI TERAI
  • Patent number: 9514807
    Abstract: A variable resistance memory device includes upper interconnections on a substrate, first and second word lines provided between the substrate and the upper interconnections and vertically spaced apart from each other, a first bit line disposed between the first and second word lines and intersecting the first and second word lines, memory cells provided in an intersecting region of the first word line and the first bit line and an intersecting region of the second word line and the first bit line, a first word line contact directly connecting the first word line to a corresponding one of the upper interconnections, and a second word line contact directly connecting the second word line to a corresponding one of the upper interconnections.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: December 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: YounSeon Kang, Jungdal Choi, Masayuki Terai, Youngbae Kim, Jung Moo Lee, Seungjae Jung
  • Publication number: 20160197121
    Abstract: A variable resistance memory device includes a plurality of first conductive layer pattern, a plurality of second conductive layer patterns over the first conductive layer patterns, and a plurality of lower cell structures including a switching element and a variable resistance element, the lower cell structures being formed at intersections at which the first conductive layer patterns and the second conductive layer patterns overlap each other. The first conductive layer patterns, the second conductive layer patterns and the lower cell structures serves as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 7, 2016
    Inventors: Jin-Woo LEE, Youn-Sean KANG, Seung-Jae JUNG, Hyun-Su JU, Masayuki TERAI
  • Publication number: 20160180929
    Abstract: A variable resistance memory device includes upper interconnections on a substrate, first and second word lines provided between the substrate and the upper interconnections and vertically spaced apart from each other, a first bit line disposed between the first and second word lines and intersecting the first and second word lines, memory cells provided in an intersecting region of the first word line and the first bit line and an intersecting region of the second word line and the first bit line, a first word line contact directly connecting the first word line to a corresponding one of the upper interconnections, and a second word line contact directly connecting the second word line to a corresponding one of the upper interconnections.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 23, 2016
    Inventors: YounSeon Kang, Jungdal Choi, Masayuki Terai, Youngbae Kim, Jung Moo Lee, Seungjae Jung
  • Patent number: 9373665
    Abstract: A resistance change nonvolatile memory device, includes: a first wiring; an interlayer insulating layer formed over the first wiring; and a second wiring formed over the interlayer insulating layer, wherein the interlayer insulating layer is interposed between the first wiring and the second wiring and includes a hole having a width not greater than a width of the first wiring, wherein the resistance change nonvolatile memory device further includes a lower electrode formed at a bottom portion of the hole and contacting the first wiring; a resistance change layer formed on the lower electrode; and an upper electrode formed over the resistance change layer, wherein the lower electrode, the resistance change layer, and the upper electrode are formed inside the hole, wherein an entirety of the resistance change layer is disposed inside the hole.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: June 21, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Masayuki Terai
  • Patent number: 9362340
    Abstract: A memory device is provided. The memory device includes bit lines that extend in a first direction on a substrate, word lines configured to vertically cross the bit lines, memory cells formed at intersections of the bit lines and the word lines, a first low permittivity layer configured to fill spaces between the bit lines and partially fill spaces between the memory cells formed on bottom surfaces of the word lines, a first dielectric layer stacked on an upper surface of the first low permittivity layer between the memory cells, a second dielectric layer configured to fill spaces between the memory cells formed on upper surfaces of the bit lines, and a second low permittivity layer stacked on an upper surface of the second dielectric layer and configured to fill spaces between the word lines. The first and second low permittivity layers have lower permittivity than the first and second dielectric layers.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: June 7, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Masayuki Terai, Jung-Moo Lee
  • Publication number: 20160099051
    Abstract: A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. A material for the second electrode includes one of members selected from the group consisting of W, Ti, Ta, and nitrides thereof. During forming of the resistance change device, the control circuit performs a second forming treatment succeeding to a first forming treatment. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.
    Type: Application
    Filed: December 14, 2015
    Publication date: April 7, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Tomonori SAKAGUCHI, Masayuki TERAI, Koichi YAKO
  • Patent number: 9305641
    Abstract: A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. A material for the second electrode includes one of members selected from the group consisting of W, Ti, Ta, and nitrides thereof. During forming of the resistance change device, the control circuit performs a second forming treatment succeeding to a first forming treatment. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: April 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Tomonori Sakaguchi, Masayuki Terai, Koichi Yako
  • Patent number: 9263673
    Abstract: A resistive memory device includes a switching device disposed on a lower interconnection, a resistor element disposed on the switching device, and an upper interconnection disposed on the resistor element. The switching device includes a diode electrode, a high-concentration lower anode disposed on the diode electrode, a middle-concentration lower anode disposed on the lower high-concentration anode electrode, a common cathode disposed on the middle-concentration lower anode, a low-concentration upper anode disposed on the common cathode, and an high-concentration upper anode disposed on the low-concentration upper anode. The peak dopant concentration of the middle-concentration lower anode is at least 10 times greater than the peak dopant concentration of the low-concentration upper anode.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Masayuki Terai, In-Gyu Baek
  • Publication number: 20150372229
    Abstract: A resistive memory device includes a switching device disposed on a lower interconnection, a resistor element disposed on the switching device, and an upper interconnection disposed on the resistor element. The switching device includes a diode electrode, a high-concentration lower anode disposed on the diode electrode, a middle-concentration lower anode disposed on the lower high-concentration anode electrode, a common cathode disposed on the middle-concentration lower anode, a low-concentration upper anode disposed on the common cathode, and an high-concentration upper anode disposed on the low-concentration upper anode. The peak dopant concentration of the middle-concentration lower anode is at least 10 times greater than the peak dopant concentration of the low-concentration upper anode.
    Type: Application
    Filed: January 30, 2015
    Publication date: December 24, 2015
    Inventors: MASAYUKI TERAI, IN-GYU BAEK
  • Publication number: 20150372060
    Abstract: A memory device is provided. The memory device includes bit lines that extend in a first direction on a substrate, word lines configured to vertically cross the bit lines, memory cells formed at intersections of the bit lines and the word lines, a first low permittivity layer configured to fill spaces between the bit lines and partially fill spaces between the memory cells formed on bottom surfaces of the word lines, a first dielectric layer stacked on an upper surface of the first low permittivity layer between the memory cells, a second dielectric layer configured to fill spaces between the memory cells formed on upper surfaces of the bit lines, and a second low permittivity layer stacked on an upper surface of the second dielectric layer and configured to fill spaces between the word lines. The first and second low permittivity layers have lower permittivity than the first and second dielectric layers.
    Type: Application
    Filed: June 9, 2015
    Publication date: December 24, 2015
    Inventors: Masayuki Terai, Jung-Moo Lee
  • Publication number: 20150357381
    Abstract: A resistance change nonvolatile memory device, includes: a first wiring; an interlayer insulating layer formed over the first wiring; and a second wiring formed over the interlayer insulating layer, wherein the interlayer insulating layer is interposed between the first wiring and the second wiring and includes a hole having a width not greater than a width of the first wiring, wherein the resistance change nonvolatile memory device further includes a lower electrode formed at a bottom portion of the hole and contacting the first wiring; a resistance change layer formed on the lower electrode; and an upper electrode formed over the resistance change layer, wherein the lower electrode, the resistance change layer, and the upper electrode are formed inside the hole, wherein an entirety of the resistance change layer is disposed inside the hole.
    Type: Application
    Filed: August 19, 2015
    Publication date: December 10, 2015
    Inventor: Masayuki TERAI
  • Patent number: 9208868
    Abstract: A memory cell is included which has a selection transistor and a variable resistance device connected to a bit line through the selection transistor. The variable resistance device includes a first electrode which has a first metal material and is connected to the selection transistor, a second electrode which has a second metal material different from the first metal material, and an insulating film which is provided between the first electrode and the second electrode, has a third metal material different from the first metal material and the second metal material, and has oxygen. The second metal material has a greater normalized oxide formation energy than the first metal material.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: December 8, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Masayuki Terai
  • Patent number: 9184218
    Abstract: A semiconductor memory device includes pillars extending upright on a substrate in a direction perpendicular to the substrate, a stack disposed on the substrate and constituted by a first interlayer insulating layer, a first conductive layer, a second interlayer insulating layer, and a second conductive layer, a variable resistance layer interposed between the pillars and the first conductive layer, and an insulating layer interposed between the first pillars and the second conductive layer.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: November 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Lijie Zhang, Young-Bae Kim, Youn-Seon Kang, In-Gyu Baek, Masayuki Terai