Abstract: Provided is a method of fabricating a memory device.

Abstract: To provide a resistance change nonvolatile memory device performing a stable switching operation at a low cost. The resistance change nonvolatile memory device has a first wiring, an interlayer insulating layer formed thereon, a second wiring formed thereon, and a resistance change element formed between the first wiring and the second wiring. The interlayer insulating layer between the first wiring and the second wiring has a hole having a width not greater than that of the first wiring. The resistance change element is in contact with the first wiring and has a lower electrode at the bottom of the hole, a resistance change layer thereon, and an upper electrode thereon. They are formed inside the hole. The first wiring contains copper and the lower electrode contains at least one metal selected from the group consisting of ruthenium, tungsten, cobalt, platinum, gold, rhodium, iridium, and palladium.

Abstract: A method of fabricating a memory device includes defining a cell region on a substrate and defining a dummy region around the cell region, forming bit lines on a top surface of the substrate, the bit lines extending in one direction, forming cell vertical structures on top surfaces of the bit lines corresponding to the cell region, each cell vertical structure including a cell diode and a variable resistive element, forming dummy vertical structures on top surfaces of the bit lines corresponding to the dummy region, each dummy vertical structure including a dummy diode and a variable resistive element, and forming word lines in contact with top surfaces of the cell vertical structures and dummy vertical structures, the word lines intersecting the bit lines at right angles.

Abstract: Provided is a method of fabricating a memory device.

Abstract: A semiconductor memory device includes pillars extending upright on a substrate in a direction perpendicular to the substrate, a stack disposed on the substrate and constituted by a first interlayer insulating layer, a first conductive layer, a second interlayer insulating layer, and a second conductive layer, a variable resistance layer interposed between the pillars and the first conductive layer, and an insulating layer interposed between the first pillars and the second conductive layer.

Abstract: A method of fabricating a memory device includes defining a cell region on a substrate and defining a dummy region around the cell region, forming bit lines on a top surface of the substrate, the bit lines extending in one direction, forming cell vertical structures on top surfaces of the bit lines corresponding to the cell region, each cell vertical structure including a cell diode and a variable resistive element, forming dummy vertical structures on top surfaces of the bit lines corresponding to the dummy region, each dummy vertical structure including a dummy diode and a variable resistive element, and forming word lines in contact with top surfaces of the cell vertical structures and dummy vertical structures, the word lines intersecting the bit lines at right angles.

Abstract: In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder type MIM structure with a first depth, and is designed for a variable resistance type memory. The capacitance element has a cylinder type MIM structure with a second depth deeper than the first depth, and is designed for a DRAM.

Abstract: In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder type MIM structure with a first depth, and is designed for a variable resistance type memory. The capacitance element has a cylinder type MIM structure with a second depth deeper than the first depth, and is designed for a DRAM.

Abstract: A memory cell is included which has a selection transistor and a variable resistance device connected to a bit line through the selection transistor. The variable resistance device includes a first electrode which has a first metal material and is connected to the selection transistor, a second electrode which has a second metal material different from the first metal material, and an insulating film which is provided between the first electrode and the second electrode, has a third metal material different from the first metal material and the second metal material, and has oxygen. The second metal material has a greater normalized oxide formation energy than the first metal material.

Abstract: Provided is a semiconductor device including: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a lower electrode contains a first metal material, an upper electrode containing a second metal material, and an insulating film containing oxygen, the first metal material has a normalized oxide formation energy higher than that of the second metal material, and the control unit applies a positive voltage to the upper electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the lower electrode at the time of an operation of reading out the resistance value of the insulating film.

Abstract: A semiconductor device includes at least first and second electrodes, and a layer including a transition metal oxide layer sandwiched between the first and second electrodes. The transition metal oxide layer includes first and second transition metal oxide layers formed of different first and second transition metals, respectively. The first transition metal oxide layer is provided on the first electrode side, the second transition metal oxide layer is provided on the second electrode side, the first transition metal oxide layer and the second transition metal oxide layer are in contact with each other, the first transition metal oxide layer has an oxygen concentration gradient from the interface between the first transition metal oxide layer and the second transition metal oxide layer toward the first electrode side, and the oxygen concentration at the interface is greater than the oxygen concentration on the first electrode side.

Abstract: A resistance change nonvolatile memory device includes with a first electrode, a resistance change portion provided on the first electrode, and a second electrode provided on the resistance change portion. The resistance change portion is equipped with a resistance change layer provided on the first electrode and undergoing a change in resistance with an applied voltage and a stable layer provided on the resistance change layer and forming a filament. The resistance change layer and the stable layer are made of metal oxides different from each other. The oxide formation energy of the resistance change layer is higher than that of the stable layer. The resistance change layer has such a film thickness as to permit the resistance of the resistance change portion in an Off state to fall within a range determined by the film thickness.

Abstract: In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate 1 a first gate lamination structure which comprises a first insulating film 11 including a trap layer, and a first conductive body 9, and a second gate lamination structure which comprises a second insulating film 12 free of a trap layer and including an insulating film layer 13 doped with metal for controlling the work function at least on the upper layer, and a second conductive body 10. A source drain region 2 and a source drain region 3 are formed such that the first gate lamination structure and the second gate lamination structure are interleaved therebetween. The effective work function of the second gate lamination structure is higher than that of the first gate lamination structure.

Abstract: A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. A material for the second electrode includes one of members selected from the group consisting of W, Ti, Ta, and nitrides thereof. During forming of the resistance change device, the control circuit performs a second forming treatment succeeding to a first forming treatment. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.

Abstract: In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder type MIM structure with a first depth, and is designed for a variable resistance type memory. The capacitance element has a cylinder type MIM structure with a second depth deeper than the first depth, and is designed for a DRAM.

Abstract: To provide a resistance change nonvolatile memory device performing a stable switching operation at a low cost. The resistance change nonvolatile memory device has a first wiring, an interlayer insulating layer formed thereon, a second wiring formed thereon, and a resistance change element formed between the first wiring and the second wiring. The interlayer insulating layer between the first wiring and the second wiring has a hole having a width not greater than that of the first wiring. The resistance change element is in contact with the first wiring and has a lower electrode at the bottom of the hole, a resistance change layer thereon, and an upper electrode thereon. They are formed inside the hole. The first wiring contains copper and the lower electrode contains at least one metal selected from the group consisting of ruthenium, tungsten, cobalt, platinum, gold, rhodium, iridium, and palladium.

Abstract: A resistance change nonvolatile memory device includes with a first electrode, a resistance change portion provided on the first electrode, and a second electrode provided on the resistance change portion. The resistance change portion is equipped with a resistance change layer provided on the first electrode and undergoing a change in resistance with an applied voltage and a stable layer provided on the resistance change layer and forming a filament. The resistance change layer and the stable layer are made of metal oxides different from each other. The oxide formation energy of the resistance change layer is higher than that of the stable layer. The resistance change layer has such a film thickness as to permit the resistance of the resistance change portion in an Off state to fall within a range determined by the film thickness.

Abstract: In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate1 a first gate lamination structure which comprises a first insulating film 11 including a trap layer, and a first conductive body 9, and a second gate lamination structure which comprises a second insulating film 12 free of a trap layer and including an insulating film layer 13 doped with metal for controlling the work function at least on the upper layer, and a second conductive body 10. A source drain region 2 and a source drain region 3 are formed such that the first gate lamination structure and the second gate lamination structure are interleaved therebetween. The effective work function of the second gate lamination structure is higher than that of the first gate lamination structure.

Abstract: A semiconductor storage device is provided for solving the problem of the inability to simultaneously realize high reliability and decreased cell area. A selection electrode (106) is formed to sandwich an insulating film (105) with a p-type semiconductor region (102). A first n-type semiconductor region (103) and a second n-type semiconductor region (104) are formed in the p-type semiconductor region (102) at two sides of the selection electrode (106). A first resistance-changing layer (107) is connected to the first n-type semiconductor region (103), and a second resistance-changing layer (109) is connected to the second n-type semiconductor region (104). In addition, a first wiring layer (108) is connected to the second resistance-changing layer (109), and a second wiring layer (110) is connected to the second resistance-changing layer (109).

Abstract: A semiconductor device includes at least first and second electrodes, and a layer including a transition metal oxide layer sandwiched between the first and second electrodes. The transition metal oxide layer includes first and second transition metal oxide layers formed of different first and second transition metals, respectively. The first transition metal oxide layer is provided on the first electrode side, the second transition metal oxide layer is provided on the second electrode side, the first transition metal oxide layer and the second transition metal oxide layer are in contact with each other, the first transition metal oxide layer has an oxygen concentration gradient from the interface between the first transition metal oxide layer and the second transition metal oxide layer toward the first electrode side, and the oxygen concentration at the interface is greater than the oxygen concentration on the first electrode side.