Abstract: In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate 1 a first gate lamination structure which comprises a first insulating film 11 including a trap layer, and a first conductive body 9, and a second gate lamination structure which comprises a second insulating film 12 free of a trap layer and including an insulating film layer 13 doped with metal for controlling the work function at least on the upper layer, and a second conductive body 10. A source drain region 2 and a source drain region 3 are formed such that the first gate lamination structure and the second gate lamination structure are interleaved therebetween. The effective work function of the second gate lamination structure is higher than that of the first gate lamination structure.

Abstract: Provided is a semiconductor device including: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a lower electrode contains a first metal material, an upper electrode containing a second metal material, and an insulating film containing oxygen, the first metal material has a normalized oxide formation energy higher than that of the second metal material, and the control unit applies a positive voltage to the upper electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the lower electrode at the time of an operation of reading out the resistance value of the insulating film.

Abstract: A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.

Abstract: Provided is a semiconductor device including: source-drain regions formed on a silicon substrate with a channel forming region sandwiched therebetween; a word gate electrode formed on the channel forming region via a word gate insulating film not including a charge storage layer; a control gate formed on the silicon substrate on one side of the word gate electrode via a trap insulating film including a charge storage layer; and a control gate formed on the silicon substrate on the other side of the word gate electrode via a trap insulating film including a charge storage layer. A bottom of the word gate electrode is made to be higher than the control gate and a bottom of the control gate, and a level difference between the bottoms of the electrodes is made to be larger than a physical film thickness of the word gate insulating film.

Abstract: A semiconductor storage device is provided for solving the problem of the inability to simultaneously realize high reliability and decreased cell area. A selection electrode (106) is formed to sandwich an insulating film (105) with a p-type semiconductor region (102). A first n-type semiconductor region (103) and a second n-type semiconductor region (104) are formed in the p-type semiconductor region (102) at two sides of the selection electrode (106). A first resistance-changing layer (107) is connected to the first n-type semiconductor region (103), and a second resistance-changing layer (109) is connected to the second n-type semiconductor region (104). In addition, a first wiring layer (108) is connected to the second resistance-changing layer (109), and a second wiring layer (110) is connected to the second resistance-changing layer (109).

Abstract: Disclosed is a resistance change type nonvolatile memory that has an insulation film structure, is advantageous for the implementation of high integration, and achieves a stable switching characteristic, and a manufacturing method therefor. The memory includes at least an MIM (Metal/Insulator/Metal) structure including an insulation film (2) sandwiched between metal electrodes (1) and (3), and the insulation film (2) includes a laminated structure including a Ta2O5 film and a TiO2 film with a thickness of less than 30 nm. The Ta2O5 film is a stoichiometric amorphous film.

Abstract: Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the semiconductor substrate via the gate insulating film. The gate insulating film has a nitrogen-containing silicon oxide film inside, and a silicon oxide film is so arranged on both sides of the nitrogen-containing silicon oxide film as to sandwich the nitrogen-containing silicon oxide film. In addition, the nitrogen composition in the nitrogen-containing silicon oxide film is increased from the semiconductor substrate side to the first gate electrode side.

Abstract: There is provided a trap memory device suppresses electric charges from flowing from the outside into a charge accumulation region and accumulated electric charges from diffusing to the outside or flowing out due to a defect. A gate conductor 6 is formed through a laminate insulating film including a first gate insulating film 3, a charge accumulation layer 4 and a second gate insulating film 5 on a silicon substrate 1. The laminate insulating film (3 to 5) projects outside the gate conductor 6 and extends to under the outer end of a side wall 8. The charge accumulation layer 4 includes a high trap surface-density region 4a immediately under the gate conductor and a low trap surface-density region 4b outside the gate conductor.

Abstract: A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.

Abstract: A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.

Abstract: In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate 1 a first gate lamination structure which comprises a first insulating film 11 including a trap layer, and a first conductive body 9, and a second gate lamination structure which comprises a second insulating film 12 free of a trap layer and including an insulating film layer 13 doped with metal for controlling the work function at least on the upper layer, and a second conductive body 10. A source drain region 2 and a source drain region 3 are formed such that the first gate lamination structure and the second gate lamination structure are interleaved therebetween. The effective work function of the second gate lamination structure is higher than that of the first gate lamination structure.

Abstract: Provided is a semiconductor device including: source-drain regions formed on a silicon substrate with a channel forming region sandwiched therebetween; a word gate electrode formed on the channel forming region via a word gate insulating film not including a charge storage layer; a control gate formed on the silicon substrate on one side of the word gate electrode via a trap insulating film including a charge storage layer; and a control gate formed on the silicon substrate on the other side of the word gate electrode via a trap insulating film including a charge storage layer. A bottom of the word gate electrode is made to be higher than the control gate and a bottom of the control gate, and a level difference between the bottoms of the electrodes is made to be larger than a physical film thickness of the word gate insulating film.

Abstract: Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the semiconductor substrate via the gate insulating film. The gate insulating film has a nitrogen-containing silicon oxide film inside, and a silicon oxide film is so arranged on both sides of the nitrogen-containing silicon oxide film as to sandwich the nitrogen-containing silicon oxide film. In addition, the nitrogen composition in the nitrogen-containing silicon oxide film is increased from the semiconductor substrate side to the first gate electrode side.

Abstract: In a case of writing to a trap type non-volatile memory cell that includes: a laminated insulating film, containing a charge accumulation layer, that is formed on a semiconductor substrate where source, drain and well regions are formed; and a first gate electrode formed on the laminated insulating film, charge injections that are carried on a single memory node multiple times under two or more different writing conditions, the writing condition is a combination of a well voltage applied to the well, a drain voltage applied to the drain and a gate voltage is applied to the first gate. Thereby, it is possible to form a trapezoid-shaped electron distribution in the charge accumulation layer, and thus prevent the charge retention characteristic from deteriorating.

Abstract: There is provided a semiconductor device including: a first field effect transistor region including a gate insulating film, a gate electrode and gate sidewalls formed in a P channel forming region; and a second field effect transistor region including a gate insulating film, a gate electrode and gate sidewalls formed in an N channel forming region on a semiconductor substrate, wherein in the first and second field effect transistor regions, the gate electrodes are composed primarily of a silicide of metal M represented as M(x)Si(1?x)(0<x<1) and satisfy t1?t2<L/2, wherein the height of the gate electrodes is t1, the height of the gate sidewalls is t2 and the gate length of the gate electrodes is L; and the height of the gate electrode in the P channel forming region is greater than the height of the gate electrode in the N channel forming region.

Abstract: There is provided a trap memory device suppresses electric charges from flowing from the outside into a charge accumulation region and accumulated electric charges from diffusing to the outside or flowing out due to a defect. A gate conductor 6 is formed through a laminate insulating film including a first gate insulating film 3, a charge accumulation layer 4 and a second gate insulating film 5 on a silicon substrate 1. The laminate insulating film (3 to 5) projects outside the gate conductor 6 and extends to under the outer end of a side wall 8. The charge accumulation layer 4 includes a high trap surface-density region 4a immediately under the gate conductor and a low trap surface-density region 4b outside the gate conductor.

Abstract: The semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 formed on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 112 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from a group consisting of Hf and Zr.

Abstract: The present invention provides an interconnection area decision processor for deciding vertical widths of areas employed for interconnection of a gate array. The interconnection area decision processor predicts which interconnection area each signal net passes on the basis of previously created data on cell arrangement and data on arrangement of transistor rows on a chip to estimate interconnection congestion per channel on the basis of the result of prediction and decide the number of transistor rows to be assigned to each channel on the basis of the estimated interconnection congestion, thereby to create data on the vertical width of each channel. Thus, density of integration can be improved by increasing the number of tracks of channels having large numbers of interconnections and decreasing the number of tracks of channels having small numbers of interconnections.