Patents by Inventor Mase J. Taub
Mase J. Taub has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170287533Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.Type: ApplicationFiled: January 25, 2017Publication date: October 5, 2017Applicant: Intel CorporationInventors: Rakesh Jeyasingh, Nevil N. Gajera, Mase J. Taub, Kiran Pangal
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Publication number: 20170229172Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: ApplicationFiled: March 21, 2017Publication date: August 10, 2017Applicant: Intel CorporationInventors: RAYMOND W. ZENG, MASE J. TAUB, KIRAN PANGAL, SANDEEP K. GULIANI
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Patent number: 9685213Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.Type: GrantFiled: November 9, 2016Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub
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Patent number: 9685204Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.Type: GrantFiled: June 22, 2016Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Mase J Taub, Sandeep K. Guliani, Kiran Pangal
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Patent number: 9601193Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: GrantFiled: September 14, 2015Date of Patent: March 21, 2017Assignee: INTEL CORPORATIONInventors: Raymond W. Zeng, Mase J. Taub, Kiran Pangal, Sandeep K. Guliani
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Publication number: 20170076794Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: ApplicationFiled: September 14, 2015Publication date: March 16, 2017Applicant: INTEL CORPORATIONInventors: RAYMOND W. ZENG, MASE J. TAUB, KIRAN PANGAL, SANDEEP K. GULIANI
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Patent number: 9589634Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.Type: GrantFiled: March 31, 2016Date of Patent: March 7, 2017Assignee: Intel CorporationInventors: Rakesh Jeyasingh, Nevil N. Gajera, Mase J Taub, Kiran Pangal
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Publication number: 20170053698Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.Type: ApplicationFiled: November 9, 2016Publication date: February 23, 2017Inventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub
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Patent number: 9543004Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.Type: GrantFiled: June 17, 2015Date of Patent: January 10, 2017Assignee: INTEL CORPORATIONInventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub
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Publication number: 20160372194Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 17, 2015Publication date: December 22, 2016Inventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub
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Publication number: 20160351258Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.Type: ApplicationFiled: May 29, 2015Publication date: December 1, 2016Applicant: Intel CorporationInventors: Mase J. Taub, Sandeep K. Guliani, Kiran Pangal, Raymond W. Zeng
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Publication number: 20160336048Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.Type: ApplicationFiled: June 22, 2016Publication date: November 17, 2016Applicant: Intel CorporationInventors: Mase J Taub, Sandeep K. Guliani, Kiran Pangal
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Patent number: 9384831Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.Type: GrantFiled: May 29, 2014Date of Patent: July 5, 2016Inventors: Mase J Taub, Sandeep K. Guliani, Kiran Pangal
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Patent number: 9224465Abstract: The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.Type: GrantFiled: March 21, 2014Date of Patent: December 29, 2015Assignee: Intel CorporationInventors: Nathan R. Franklin, Sandeep K. Guliani, Mase J. Taub, Kiran Pangal
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Publication number: 20150348627Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.Type: ApplicationFiled: May 29, 2014Publication date: December 3, 2015Inventors: Mase J Taub, Sandeep K. Guliani, Kiran Pangal
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Publication number: 20150269994Abstract: The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.Type: ApplicationFiled: March 21, 2014Publication date: September 24, 2015Applicant: Intel CorporationInventors: NATHAN R. FRANKLIN, SANDEEP K. GULIANI, MASE J. TAUB, KIRAN PANGAL
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Patent number: 8954650Abstract: Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB.Type: GrantFiled: September 16, 2011Date of Patent: February 10, 2015Assignee: Intel CorporationInventors: Hanmant P. Belgal, Ning Wu, Paul D. Ruby, Andrew Vogan, Xin Guo, Ivan Kalastirsky, Mase J. Taub
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Publication number: 20130073786Abstract: Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB.Type: ApplicationFiled: September 16, 2011Publication date: March 21, 2013Inventors: Hanmant P. Belgal, Ning Wu, Paul D. Ruby, Andrew Vogan, Xin Guo, Ivan Kalastirsky, Mase J. Taub
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Patent number: 7129770Abstract: Methods and apparatuses associated with providing a bias voltage for an n-type and a p-type device. A high voltage may be received and used to derive a bias voltage that would reduce a risk of gate-aided breakdown of the drain-to-substrate channel-side pn-junction in an n-type device. The high voltage may be used to derive a bias voltage that would reduce the risk of gate-aided breakdown of the drain-to-substrate channel-side pn-junction in a p-type device.Type: GrantFiled: June 30, 2004Date of Patent: October 31, 2006Assignee: Intel CorporationInventors: Gerald J. Barkley, Mase J. Taub
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Patent number: 6781912Abstract: An integrated power supply circuitry that supplies power in an integrated circuit to a chip may provide protection against transistor junction breakdowns from a supply voltage. For example, in a nonvolatile memory, such as a flash memory, a transistor PN-junction breakdown (e.g., a gate-aided drain-substrate PN-junction breakdown (BVD)) of metal silicon oxide (MOS) transistors may be prevented even though the supply voltage exceeds the BVD voltage limit thereof.Type: GrantFiled: December 31, 2002Date of Patent: August 24, 2004Assignee: Intel CorporationInventor: Mase J. Taub