Patents by Inventor Mase J. Taub

Mase J. Taub has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170287533
    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.
    Type: Application
    Filed: January 25, 2017
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventors: Rakesh Jeyasingh, Nevil N. Gajera, Mase J. Taub, Kiran Pangal
  • Publication number: 20170229172
    Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.
    Type: Application
    Filed: March 21, 2017
    Publication date: August 10, 2017
    Applicant: Intel Corporation
    Inventors: RAYMOND W. ZENG, MASE J. TAUB, KIRAN PANGAL, SANDEEP K. GULIANI
  • Patent number: 9685213
    Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub
  • Patent number: 9685204
    Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Mase J Taub, Sandeep K. Guliani, Kiran Pangal
  • Patent number: 9601193
    Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: March 21, 2017
    Assignee: INTEL CORPORATION
    Inventors: Raymond W. Zeng, Mase J. Taub, Kiran Pangal, Sandeep K. Guliani
  • Publication number: 20170076794
    Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.
    Type: Application
    Filed: September 14, 2015
    Publication date: March 16, 2017
    Applicant: INTEL CORPORATION
    Inventors: RAYMOND W. ZENG, MASE J. TAUB, KIRAN PANGAL, SANDEEP K. GULIANI
  • Patent number: 9589634
    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 7, 2017
    Assignee: Intel Corporation
    Inventors: Rakesh Jeyasingh, Nevil N. Gajera, Mase J Taub, Kiran Pangal
  • Publication number: 20170053698
    Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: November 9, 2016
    Publication date: February 23, 2017
    Inventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub
  • Patent number: 9543004
    Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: January 10, 2017
    Assignee: INTEL CORPORATION
    Inventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub
  • Publication number: 20160372194
    Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 22, 2016
    Inventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub
  • Publication number: 20160351258
    Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 1, 2016
    Applicant: Intel Corporation
    Inventors: Mase J. Taub, Sandeep K. Guliani, Kiran Pangal, Raymond W. Zeng
  • Publication number: 20160336048
    Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.
    Type: Application
    Filed: June 22, 2016
    Publication date: November 17, 2016
    Applicant: Intel Corporation
    Inventors: Mase J Taub, Sandeep K. Guliani, Kiran Pangal
  • Patent number: 9384831
    Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: July 5, 2016
    Inventors: Mase J Taub, Sandeep K. Guliani, Kiran Pangal
  • Patent number: 9224465
    Abstract: The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Nathan R. Franklin, Sandeep K. Guliani, Mase J. Taub, Kiran Pangal
  • Publication number: 20150348627
    Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 3, 2015
    Inventors: Mase J Taub, Sandeep K. Guliani, Kiran Pangal
  • Publication number: 20150269994
    Abstract: The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.
    Type: Application
    Filed: March 21, 2014
    Publication date: September 24, 2015
    Applicant: Intel Corporation
    Inventors: NATHAN R. FRANKLIN, SANDEEP K. GULIANI, MASE J. TAUB, KIRAN PANGAL
  • Patent number: 8954650
    Abstract: Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: February 10, 2015
    Assignee: Intel Corporation
    Inventors: Hanmant P. Belgal, Ning Wu, Paul D. Ruby, Andrew Vogan, Xin Guo, Ivan Kalastirsky, Mase J. Taub
  • Publication number: 20130073786
    Abstract: Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Inventors: Hanmant P. Belgal, Ning Wu, Paul D. Ruby, Andrew Vogan, Xin Guo, Ivan Kalastirsky, Mase J. Taub
  • Patent number: 7129770
    Abstract: Methods and apparatuses associated with providing a bias voltage for an n-type and a p-type device. A high voltage may be received and used to derive a bias voltage that would reduce a risk of gate-aided breakdown of the drain-to-substrate channel-side pn-junction in an n-type device. The high voltage may be used to derive a bias voltage that would reduce the risk of gate-aided breakdown of the drain-to-substrate channel-side pn-junction in a p-type device.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: Gerald J. Barkley, Mase J. Taub
  • Patent number: 6781912
    Abstract: An integrated power supply circuitry that supplies power in an integrated circuit to a chip may provide protection against transistor junction breakdowns from a supply voltage. For example, in a nonvolatile memory, such as a flash memory, a transistor PN-junction breakdown (e.g., a gate-aided drain-substrate PN-junction breakdown (BVD)) of metal silicon oxide (MOS) transistors may be prevented even though the supply voltage exceeds the BVD voltage limit thereof.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: August 24, 2004
    Assignee: Intel Corporation
    Inventor: Mase J. Taub