Abstract: An integrated power supply circuitry that supplies power in an integrated circuit to a chip may provide protection against transistor junction breakdowns from a supply voltage. For example, in a nonvolatile memory, such as a flash memory, a transistor PN-junction breakdown (e.g., a gate-aided drain-substrate PN-junction breakdown (BVD)) of metal silicon oxide (MOS) transistors may be prevented even though the supply voltage exceeds the BVD voltage limit thereof.

Abstract: A level shifter may be utilized in a flash memory to reduce the standby power consumption. The level shifter may be coupled so that the gate-to-source voltage of the input transistor is reduced during standby operations to reduce leakage current. At the same time, the source of the input transistor may be coupled to a lower voltage during active level shifting operations. Thus, good transistor characteristics may be achieved with reduced leakage currents.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

Abstract: A method and apparatus to segment a programmable non-volatile memory array into at least two banks. The banks include memory cells. Each bank in the at least two banks is provided with a local programming voltage. Each local programming voltage is independent of the other local programming voltages supplied to the other banks.

Abstract: A level shifter may be utilized in a flash memory to reduce the standby power consumption. The level shifter may be coupled so that the gate-to-source voltage of the input transistor is reduced during standby operations to reduce leakage current. At the same time, the source of the input transistor may be coupled to a lower voltage during active level shifting operations.

Abstract: A circuit includes (i) an N-channel device having a gate, a source connected to low voltage, and a drain connected to a memory select gate, (ii) a P-channel device having a gate, a source, and a drain connected to the drain of the N-channel device, and (iii) a voltage supply connected to the source of the P-channel device, the voltage supply switching between a first high voltage and a first lower voltage. A gate driver supplies, to the gates of the N-channel and P-channel devices, a second high voltage, a second low voltage, or an intermediary voltage between the second high voltage and second low voltage. The gate driver supplies the intermediary voltage when the voltage supply switches between the first high voltage and first lower voltage.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

Abstract: A level shifter may be utilized in a flash memory to reduce the standby power consumption. The level shifter may be coupled so that the gate-to-source voltage of the input transistor is reduced during standby operations to reduce leakage current. At the same time, the source of the input transistor may be coupled to a lower voltage during active level shifting operations. Thus, good transistor characteristics may be achieved with reduced leakage currents.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.

Abstract: A scaleable charge pump. The charge pump is configured on an integrated circuit device that operates at a supply voltage and includes a predetermined number of pump stages coupled in series, at least one of the stages being coupled to receive a first pumped clock signal. An output node coupled in series to one end of the predetermined number of series coupled pump stages provides a pumped output voltage.

Abstract: A reconfigurable charge pump is disclosed. A gated pumped output diode is coupled between the outputs of an intermediate pump stage and a final pump stage of the reconfigurable charge pump. When a control signal is in a first state, the gated pumped output diode is placed in a non-conducting state to prevent back conduction of current from the output of the final pump stage to the intermediate pump stage. When the control signal is in a second state, the gated pumped output diode is placed in a transparent state to conduct current from the output of the intermediate pump stage to an output of the reconfigurable charge pump.

Abstract: A power supply lockout circuit that prevents corruption of nonvolatile writeable memory data is described. The power supply lockout circuit monitors the power supply signals from several power supplies. The power supply lockout circuit locks out commands writing to the nonvolatile writeable memory when any one of the monitored power supply signals coupled to the nonvolatile writeable memory is below a specified signal level. The power supply lockout circuit includes a detector which provides a lockout signal to the nonvolatile writeable memory when a power supply signal is less than a prespecified voltage. The power supply lockout circuit also includes a sampling circuit which provides other lockout signals to the nonvolatile writeable memory when a different power supply signal is less than a reference voltage.

Abstract: A method and apparatus for detecting the power supply voltage level of a circuit. A control circuit is used to enable or disable a first voltage level detector circuit and a second voltage level detector circuit. The first voltage level detector circuit consumes less power than the second voltage level detector circuit. The first voltage level detector circuit is enabled during all user modes of operation. The second voltage level detector circuit is enabled during the normal or active mode of operation and during power-up in all user modes of operation. The second voltage level detector circuit may also be enabled during a reduced power mode of operation that does not consume the least amount of power. A select circuit selects the output from either the first voltage level detector or the second voltage level detector. The first voltage level detector circuit is selected during the user mode that consumes the least amount of power.

Abstract: A voltage detector circuit for detecting when an input voltage exceeds a trip-point voltage. The voltage detector circuit includes a nonvolatile memory cell having a select gate coupled to the input voltage, a drain coupled to a first node, a source coupled to system ground, and a floating gate. The nonvolatile memory cell is used primarily as a pull-down transistor, and the threshold voltage of nonvolatile memory is programmed to be the trip-point voltage such that the first node is set to system ground if the input voltage exceeds the trip-point voltage. The voltage detector circuit also includes a first transistor having a control electrode coupled to a biasing voltage, a first terminal coupled to the first node, and a second terminal coupled to a supply voltage. The control electrode is operative to couple the first terminal to the second terminal in response to the biasing voltage. The first transistor sets the first node to the input voltage if the input voltage is less than the trip-point voltage.

Abstract: An integrated circuit including an operating circuit portion which requires a predetermined voltage in order to function properly, a charge pump circuit for providing a high voltage output equal to the predetermined voltage from a lower voltage input, a terminal for receiving voltage from a source of external voltage, and a circuit for selectively providing voltage to the operating circuit portion of the integrated circuit from the terminal if the level of voltage detected at the terminal from the external voltage source is above the predetermined voltage and for providing voltage to the operating circuit portion from the output of the charge pump if the voltage detected at the terminal is less than the predetermined level.

Abstract: An integrated circuit including an operating circuit portion which requires a predetermined voltage in order to function properly, a charge pump circuit for providing a high voltage output equal to the predetermined voltage from a lower voltage input, a terminal for receiving voltage from a source of external voltage, and a circuit for selectively providing voltage to the operating circuit portion of the integrated circuit from the terminal if the level of voltage detected at the terminal from the external voltage source is above the predetermined voltage and for providing voltage to the operating circuit portion from the output of the charge pump if the voltage detected at the terminal is less than the predetermined level.