Abstract: According to one embodiment, a semiconductor memory device includes first-third conductive layers, a semiconductor layer, a resistance change layer and a metal-containing layer. The second conductive layer is separated from the first conductive layer in a first direction. The semiconductor layer is provided between the first and the second conductive layers. The third conductive layer is arranged with the first semiconductor layer in a direction crossing the first direction. The first resistance change layer is provided between the first semiconductor layer and the first conductive layer. The first metal-containing layer is provided between the first resistance change layer and the first conductive layer. The first conductive layer extends in a second direction crossing the first direction. The second conductive layer extends in a third direction crossing the first direction and crossing the second direction. The third conductive layer extends in a direction crossing the first direction.

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first structure having a first insulating layer, a semiconductor layer, and a second insulating layer stacked in this order in a first direction, the first structure extending in a second direction, memory cells provided on a surface of the semiconductor layer facing in a third direction, and connected in series in the second direction, and a third insulating layer contacting at least one of first and second end portions of the first structure in the second direction and not covering at least a part of an area between the first and second end portions. A lattice spacing of semiconductor atoms in the semiconductor layer in the second direction is larger than a lattice spacing of the semiconductor atoms in the semiconductor layer in the first direction.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a first electrode. The third semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode opposes the third semiconductor layer. An orientation ratio of the third semiconductor layer is higher than an orientation ratio of the first semiconductor layer.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array disposed on the semiconductor substrate, a capacitor and a control circuit. The memory cell array includes a plurality of memory cells. The control circuit supplies a voltage to the memory cell array. The memory cell array includes a first conductive body disposed in a first region on the semiconductor substrate. The first conductive body extends in a first direction intersecting with a surface of the substrate. The capacitor includes first and second electrodes disposed in a second region different from the first region on the semiconductor substrate. The electrodes each include a second conductive body extending in the first direction. The first conductive body and the second conductive body include an identical material.

Abstract: A semiconductor device of an embodiment includes: an insulating film including: a first region extending in a first direction; second and third regions arranged at a distance from each other; and fourth and fifth regions each having a concave shape, the fourth and fifth regions each having a smaller film thickness than a film thickness of each of the first through third regions; a semiconductor layer formed in a direction from the fourth region toward the fifth region, the semiconductor layer having a smaller width than a width of each of source and drain regions, the semiconductor layer being connected to the source and drain regions; a gate electrode placed on the opposite side of a gate insulating film from the semiconductor layer on the first region; and a gate sidewall formed on a side face of the gate electrode.

Abstract: A storage device of an embodiment includes a first conductive layer containing a first element selected from the group consisting of Si, Ge, and a metal element, a second conductive layer including a first region containing a first metal element and carbon or nitrogen, a second region containing a second metal element and carbon or nitrogen, and a third region provided between the first region and the second region, the third region containing a third metal element, the standard free energy of formation of an oxide of the third metal element being smaller than the standard free energy of formation of an oxide of the first element, a ferroelectric layer provided between the first conductive layer and the second conductive layer, and a paraelectric layer provided between the first conductive layer and the ferroelectric layer.

Abstract: According to one embodiment, a memory device includes a first stacked layer structure stacked in order of a first insulating layer, a first electrode layer, . . . an n-th insulating layer, an n-th electrode layer, and an (n+1)-th insulating layer in a first direction perpendicular to a surface of a semiconductor substrate, where n is a natural number, an oxide semiconductor layer extending through the first to n-th electrode layers in the first direction, a second stacked layer structure provided between the first to n-th electrode layers and the oxide semiconductor layer, and including a charge storage layer which storages charges, and a area provided in the oxide semiconductor layer.

Abstract: A semiconductor integrated circuit according to an embodiment includes: a CMOS inverter including an n-channel transistor and a p-channel transistor, one of the n-channel transistor and the p-channel transistor being disposed above the other of the n-channel transistor and the p-channel transistor.

Abstract: According to one embodiment, a memory device includes a first layer, a second layers, a third layer provided between the first layer and the second layer, and first electrodes. The first layer includes first interconnections and a first insulating portion provided between the first interconnections. The second layer includes second interconnections and a second insulating portion provided between the second interconnections. The third layer includes first and second portions including silicon oxide. The first portion is provided between the first and the second interconnections. The second portion is provided between the first and the second insulating portions. The first electrodes are provided between the first interconnections and the first portion, and include a first material. The second interconnections include a second material. The first material is easier to ionize than the second material. A density of the first portion is lower than a density of the second portion.

Abstract: This nonvolatile semiconductor memory device comprises: a memory cell array including memory cells; and a wiring line portion connecting the memory cell array to an external circuit. The memory cell array comprises a plurality of first conductive layers which are connected to the memory cells and arranged in a stacking direction. On the other hand, the wiring line portion comprises: a plurality of second conductive layers arranged in the stacking direction and respectively connected to the plurality of first conductive layers, positions of ends of the plurality of second conductive layers being different in a first direction crossing the stacking direction; a third conductive layer extending in the stacking direction from the second conductive layer; a channel semiconductor layer connected to one end of the third conductive layer; and a gate electrode wiring line disposed on a surface of the channel semiconductor layer via a gate insulating film.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first wirings, second wirings, a plurality of memory cells, selection gate transistors, and a third wiring. The first wirings are disposed in a first direction along a surface of a substrate and in a second direction intersecting with the surface of the substrate. The selection gate transistors are connected to respective one ends of the second wirings. The third wiring is connected in common to one end of the selection gate transistors. The selection gate transistor includes first to third semiconductor layers laminated on the third wiring and a gate electrode. The gate electrode is opposed to the second semiconductor layer in the first direction. The second semiconductor layer has a length in the first direction smaller than lengths of the first semiconductor layer and the third semiconductor layer in the first direction.

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.

Abstract: A semiconductor device according to an embodiment includes a first region including an oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn), a second region and a third region between which the first region is disposed, at least one of the second region and the third region having a higher indium (In) concentration than the first region and containing at least one metal element from the group consisting of titanium (Ti), tungsten (W), copper (Cu), zinc (Zn), aluminum (Al), lead (Pb), and tin (Sn), an electrode; and an insulating layer disposed between the first region and the electrode.

Abstract: An imaging element according to embodiments may comprise a plurality of photoreceivers (11a), a plurality of scanning circuits (11b), a first wiring (L2), a plurality of second wirings (L1), and at least one variable resistance element (VR2). The plurality of scanning circuits (11b) may be connected to the plurality of photoreceivers, respectively. Each of the second wirings (L1) may branch off from the first wiring and be connected to one of the scanning circuits. The at least one variable resistance element (VR2) may be located on the first wiring so as to electrically intervene between adjacent branching points (N1, N2) among a plurality of branching points between the first wiring and the second wirings.

Abstract: According to an embodiment, a semiconductor device includes an underlying layer and a plurality of transistors. The underlying layer includes a first region and a second region provided adjacently to the first region. The transistors are arranged in a plane parallel to an upper surface of the underlying layer. Each transistor includes a channel allowing a current to flow in a first direction intersecting the plane. The plurality of transistors includes a first transistor provided on the first region and a second transistor provided on the second region, a first channel of the first transistor having a first crystal orientation, and a second channel of the second transistor having a second crystal orientation different from the first crystal orientation.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array disposed on the semiconductor substrate, a capacitor and a control circuit. The memory cell array includes a plurality of memory cells. The control circuit supplies a voltage to the memory cell array. The memory cell array includes a first conductive body disposed in a first region on the semiconductor substrate. The first conductive body extends in a first direction intersecting with a surface of the substrate. The capacitor includes first and second electrodes disposed in a second region different from the first region on the semiconductor substrate. The electrodes each include a second conductive body extending in the first direction. The first conductive body and the second conductive body include an identical material.

Abstract: According to one embodiment, a nonvolatile memory device includes a first metal layer, a second metal layer, a first layer, a second layer, and a third layer. The first metal layer contains at least one first metal selected from the group consisting of Al, Ni, Ti, Co, Mg, Cr, Mn, Zn, and In. The second metal layer contains at least one second metal selected from the group consisting of Ag, Cu, Fe, Sn, Pb, and Bi. The first layer is provided between the first metal layer and the second metal layer, and contains a first oxide. The second layer is provided between the first layer and the second metal layer, and contains a second oxide. The third layer is provided between the first layer and the second layer, and contains one of a silicon oxide, a silicon nitride, and a silicon oxynitride.

Abstract: A semiconductor memory device comprises: a memory cell array comprising first wiring lines, second wiring lines extending crossing the first wiring lines, and memory cells at intersections of the first and second wiring lines, the memory cells being stacked perpendicularly to a substrate, each memory cell comprising a variable resistance element; a first select transistor layer comprising a first select transistor operative to select one of the first wiring lines; a second select transistor layer comprising a second select transistor operative to select one of the second wiring lines; and a peripheral circuit layer on the substrate, the peripheral circuit layer comprising a peripheral circuit that controls a voltage applied to one of the memory cells. The first select transistor layer is provided below the memory cell array perpendicularly to the substrate. The second select transistor layer is provided above the memory cell array perpendicularly to the substrate.

Abstract: According to one embodiment, a resistance change memory includes a first conductive line, a second conductive line provided above the first conductive line, and extending in a first direction, a third conductive line extending in a second direction intersecting the first direction, a select transistor provided between the first and third conductive lines, and a resistance change layer provided between the second and third conductive lines.