Patents by Inventor Masumi Saitoh
Masumi Saitoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120273747Abstract: According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide.Type: ApplicationFiled: April 27, 2012Publication date: November 1, 2012Inventors: Masumi SAITOH, Toshinori NUMATA, Kiwamu SAKUMA, Haruka KUSAI, Takayuki ISHIKAWA
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Publication number: 20120235152Abstract: A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions.Type: ApplicationFiled: September 19, 2011Publication date: September 20, 2012Inventors: Kensuke OTA, Masumi Saitoh, Toshinori Numata
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Publication number: 20120146053Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls.Type: ApplicationFiled: September 20, 2011Publication date: June 14, 2012Inventors: Masumi SAITOH, Toshinori Numata, Yukio Nakabayashi, Kensuke Ota
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Publication number: 20120075928Abstract: In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i?1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where āiā is a positive integer and identifies a specific location to which information is to be written.Type: ApplicationFiled: September 28, 2011Publication date: March 29, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Jun Fujiki, Kiwamu Sakuma, Naoki Yasuda, Yukio Nakabayashi, Masumi Saitoh
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Publication number: 20120037994Abstract: A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.Type: ApplicationFiled: October 27, 2011Publication date: February 16, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masumi SAITOH, Ken UCHIDA
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Publication number: 20110303972Abstract: A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.Type: ApplicationFiled: April 7, 2011Publication date: December 15, 2011Inventors: Masumi SAITOH, Toshinori Numata, Yukio Nakabayashi
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Patent number: 8076231Abstract: A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.Type: GrantFiled: March 11, 2009Date of Patent: December 13, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masumi Saitoh, Ken Uchida
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Patent number: 8053758Abstract: A semiconductor device for correcting an input signal and outputting a corrected signal are provided. The semiconductor device includes a semiconductor layer, a plurality of first conductors formed on one of faces of the semiconductor layer and serving as input terminals to which a signal is input, second conductors of the number larger than that of the first conductors at density higher than that of the first conductors, formed on the other face of the semiconductor layer, a high impurity concentration region provided on the semiconductor layer side of an interface between the second conductor and the semiconductor layer, an insulating layer formed on the other face, and a plurality of third conductors formed on the insulating layer and serving as output terminals for outputting the processed signal.Type: GrantFiled: August 27, 2009Date of Patent: November 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamauchi, Yoshifumi Nishi, Hiroto Honda, Kei Masunishi, Shinji Murai, Masumi Saitoh
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Patent number: 8039887Abstract: A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.Type: GrantFiled: May 5, 2010Date of Patent: October 18, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masumi Saitoh, Ken Uchida
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Publication number: 20100213533Abstract: A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.Type: ApplicationFiled: May 5, 2010Publication date: August 26, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Masumi SAITOH, Ken Uchida
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Patent number: 7737486Abstract: A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.Type: GrantFiled: September 21, 2007Date of Patent: June 15, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masumi Saitoh, Ken Uchida
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Publication number: 20100051906Abstract: A semiconductor device for correcting an input signal and outputting a corrected signal are provided. The semiconductor device includes a semiconductor layer, a plurality of first conductors formed on one of faces of the semiconductor layer and serving as input terminals to which a signal is input, second conductors of the number larger than that of the first conductors at density higher than that of the first conductors, formed on the other face of the semiconductor layer, a high impurity concentration region provided on the semiconductor layer side of an interface between the second conductor and the semiconductor layer, an insulating layer formed on the other face, and a plurality of third conductors formed on the insulating layer and serving as output terminals for outputting the processed signal.Type: ApplicationFiled: August 27, 2009Publication date: March 4, 2010Inventors: Takashi Yamauchi, Yoshifumi Nishi, Hiroto Honda, Kei Masunishi, Shinji Murai, Masumi Saitoh
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Patent number: 7605422Abstract: A semiconductor device capable of realizing low-voltage drivability and large storage capacity (miniaturization) by achieving large threshold voltage shifts and long retention time while at the same time suppressing variations in characteristics among memory cells is disclosed. The device includes a semiconductor memory cell having a channel region formed in a semiconductor substrate, a tunnel insulator film on the channel region, a charge storage insulator film on the tunnel insulator film, a control dielectric film on the charge storage film, a control electrode on the control dielectric film, and source/drain regions at opposite ends of the channel region. The memory cell's channel region has a cross-section at right angles to a direction along the channel length, the width W and height H of which are each less than or equal to 10 nm.Type: GrantFiled: August 29, 2007Date of Patent: October 20, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Masumi Saitoh, Ken Uchida
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Publication number: 20090242990Abstract: A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.Type: ApplicationFiled: March 11, 2009Publication date: October 1, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masumi SAITOH, Ken UCHIDA
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Publication number: 20080149991Abstract: A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.Type: ApplicationFiled: September 21, 2007Publication date: June 26, 2008Inventors: Masumi SAITOH, Ken UCHIDA
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Publication number: 20080054346Abstract: A semiconductor device capable of realizing low-voltage drivability and large storage capacity (miniaturization) by achieving large threshold voltage shifts and long retention time while at the same time suppressing variations in characteristics among memory cells is disclosed. The device includes a semiconductor memory cell having a channel region formed in a semiconductor substrate, a tunnel insulator film on the channel region, a charge storage insulator film on the tunnel insulator film, a control dielectric film on the charge storage film, a control electrode on the control dielectric film, and source/drain regions at opposite ends of the channel region. The memory cell's channel region has a cross-section at right angles to a direction along the channel length, the width W and height H of which are each less than or equal to 10 nm.Type: ApplicationFiled: August 29, 2007Publication date: March 6, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Masumi SAITOH, Ken Uchida