Abstract: A method for managing network service response times by a client device is provided. The client device determines whether a network service of a service provider is reachable or active and determines a service response time of the service provider. The client device communicates to the service provider a request to establish a conditional connection based on an average accept service time of a connection and a maximum service response time.

Abstract: Described are techniques for grouping user profiles onto Virtual Private Networks (VPNs) including a computer-implemented method comprising creating a user profile at a VPN manager and associating the user profile with a set of demographically similar user profiles based on characteristics of the user profile. The computer-implemented method further comprises assigning the user profile to least one VPN server that is associated with the set of demographically similar user profiles. The computer-implemented method further comprises providing encrypted internet access to a device associated with the user profile via the at least on VPN server. The computer-implemented method further comprises transmitting resources to the device associated with the user profile via the at least one VPN server, where the resources are customized for the set of demographically similar user profiles.

Abstract: Disclosed is a computer implemented method to manage a cache, the method comprising, determining that a primary application opens a first file, wherein opening the first file includes reading the first file into a file cache from a storage. The method also includes, setting a first monitoring variable in the primary application process proc structure, wherein the first monitoring variable is set in response to the primary application opening the first file, and the first monitoring variable records a set of operations completed on the first file by the primary application. The method comprises a first read of the first file being at a beginning of the first file. The method includes identifying that the first file is read according to a pattern that includes reading the first file sequentially and reading the first file entirely and removing the first file from the file cache.

Abstract: A method for optimization of low-level memory operations in a distributed memory storage configuration that includes receiving, at a first processor, a request to migrate data from the first processor to a second processor, where the first processor and the second processor comprise a processor and memory, and identifying a command instruction associated with the requested data. The method also includes comparing a first performance metric associated with the first processor to a second performance metric associated with the second processor, where the first performance metric and the second performance metric are associated with executing the command instruction, and where, based on the comparing, a decision to move the command instruction to the second processor is formed, and migrating, responsive to the decision, the data and the command instruction to the second processor.

Abstract: Embodiments include method, systems and computer program products for switching between interrupt context input/output I/O processing versus thread context I/O processing. The method includes receiving, by a processor of a plurality of processors, an interrupt. A device driver for an I/O adapter determines that the dispatch latency for an associated kernel thread is greater than a first predetermined threshold. An adapter switches to an interrupt context mode. The adapter processes an I/O on the processor associated with the received interrupt to completion.

Abstract: A method for determining affinity domain information based on virtual memory address in a computing system where access to memory is non-uniform includes receiving a request to identify an affinity domain associated with a specified virtual memory address. The affinity domain includes a cluster of processors and memory local to the cluster of processors. A physical memory page corresponding to the specified virtual memory address is determined using a page table mapping a plurality of virtual memory addresses to a plurality of physical addresses. An affinity domain associated with the determined physical memory page is identified. Affinity domain information is provided for the identified affinity domain.

Abstract: A method for optimization of low-level memory operations in a distributed memory storage configuration that includes receiving, at a first processor, a request to migrate data from the first processor to a second processor, where the first processor and the second processor comprise a processor and memory, and identifying a command instruction associated with the requested data. The method also includes comparing a first performance metric associated with the first processor to a second performance metric associated with the second processor, where the first performance metric and the second performance metric are associated with executing the command instruction, and where, based on the comparing, a decision to move the command instruction to the second processor is formed, and migrating, responsive to the decision, the data and the command instruction to the second processor.

Abstract: Disclosed is a computer implemented method to manage a cache, the method comprising, determining that a primary application opens a first file, wherein opening the first file includes reading the first file into a file cache from a storage. The method also includes, setting a first monitoring variable in the primary application process proc structure, wherein the first monitoring variable is set in response to the primary application opening the first file, and the first monitoring variable records a set of operations completed on the first file by the primary application. The method comprises a first read of the first file being at a beginning of the first file. The method includes identifying that the first file is read according to a pattern that includes reading the first file sequentially and reading the first file entirely and removing the first file from the file cache.

Abstract: Examples of techniques for deferred disclaim of memory pages are described herein. An aspect includes, based on freeing of a last allocation on a first memory page, placing, by a processor, the first memory page on a deferred disclaim list. Another aspect includes, based on freeing of the last allocation on the first memory page, setting, by the processor, a first hidden flag in a first page table entry corresponding to the first memory page.

Abstract: Examples of techniques for hardware thread switching for scheduling policy in a processor are described herein. An aspect includes, based on receiving a request from a first software thread to dispatch to a first hardware thread, determining that the first hardware thread is occupied by a second software thread that has a higher priority than the first software thread. Another aspect includes issuing an interrupt to switch the second software thread from the first hardware thread to a second hardware thread. Another aspect includes, based on switching of the second software thread from the first hardware thread to the second hardware thread, dispatching the first software thread to the first hardware thread.

Abstract: Examples of techniques for hardware thread switching for scheduling policy in a processor are described herein. An aspect includes, based on receiving a request from a first software thread to dispatch to a first hardware thread, determining that the first hardware thread is occupied by a second software thread that has a higher priority than the first software thread. Another aspect includes issuing an interrupt to switch the second software thread from the first hardware thread to a second hardware thread. Another aspect includes, based on switching of the second software thread from the first hardware thread to the second hardware thread, dispatching the first software thread to the first hardware thread.

Abstract: A method for determining affinity domain information based on virtual memory address in a computing system where access to memory is non-uniform includes receiving a request to identify an affinity domain associated with a specified virtual memory address. The affinity domain includes a cluster of processors and memory local to the cluster of processors. A physical memory page corresponding to the specified virtual memory address is determined using a page table mapping a plurality of virtual memory addresses to a plurality of physical addresses. An affinity domain associated with the determined physical memory page is identified. Affinity domain information is provided for the identified affinity domain.

Abstract: Examples of techniques for deferred disclaim of memory pages are described herein. An aspect includes, based on freeing of a last allocation on a first memory page, placing, by a processor, the first memory page on a deferred disclaim list.

Abstract: Embodiments include method, systems and computer program products for switching between interrupt context input/output I/O processing versus thread context I/O processing. The method includes receiving, by a processor of a plurality of processors, an interrupt. A device driver for an I/O adapter determines that the dispatch latency for an associated kernel thread is greater than a first predetermined threshold. An adapter switches to an interrupt context mode. The adapter processes an I/O on the processor associated with the received interrupt to completion.

Abstract: A method for managing network service response times by a client device is provided. The client device determines whether a network service of a service provider is reachable or active and determines a service response time of the service provider. The client device communicates to the service provider a request to establish a conditional connection based on an average accept service time of a connection and a maximum service response time.

Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.

Abstract: Techniques for preserving memory affinity in a computer system is disclosed. In response to a request for memory access to a page within a memory affinity domain, a determination is made if the request is initiated by a processor associated with the memory affinity domain. If the request is not initiated by a processor associated with the memory affinity domain, a determination is made if there is a page ID match with an entry within a page migration tracking module associated with the memory affinity domain. If there is no page ID match, an entry is selected within the page migration tracking module to be updated with a new page ID and a new memory affinity ID. If there is a page ID match, then another determination is made whether or not there is a memory affinity ID match with the entry with the page ID field match. If there is no memory affinity ID match, the entry is updated with a new memory affinity ID; and if there is a memory affinity ID match, an access counter of the entry is incremented.

Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.

Abstract: Techniques are disclosed for managing lock contention in a multithreaded processing system. In one embodiment, a method includes tracking a current total amount of time that one or more software threads are prevented from execution due to a lock, a current utilization of one or more hardware threads in the processor, and a current number of dispatchable software threads. If the current total amount of time exceeds a predetermined threshold, the method includes performing a comparison of the current total amount of time, the current utilization, and the current number of dispatchable software threads to one or more past measurements. Based on the comparison, the method includes determining if reducing a number of active hardware threads will reduce a wait time. If reducing the number of active hardware threads will reduce the wait time, reducing the number of active hardware threads.

Abstract: Techniques are disclosed for managing lock contention in a multithreaded processing system. In one embodiment, a method includes tracking an amount of time that a lock on a first thread prevents a second thread from execution. The method also includes, if the amount of time is greater than a first threshold, storing the amount of time and an address associated with the lock. The method includes dispatching a third thread that utilizes the address associated with the lock. The method also includes increasing the hardware priority of the third thread during a lock operation.