Patents by Inventor Mathew Accapadi
Mathew Accapadi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10019392Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.Type: GrantFiled: June 11, 2015Date of Patent: July 10, 2018Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 10019391Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.Type: GrantFiled: March 20, 2015Date of Patent: July 10, 2018Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 9928157Abstract: A method for filtering multiple in-memory trace buffers for event ranges is provided. The method includes allocating a plurality of main trace buffers, based on the number of central processing units (CPU) participating in a trace. Each CPU has a dedicated main trace buffer, and each main trace buffer is circular. Each main trace buffer is divided into an equal number of sub-buffers. A plurality of events is written to the current sub-buffer. When the current sub-buffer is filled, events are written to the next sub-buffer. Events are extracted from at least one of the sub-buffers, starting with the sub-buffer that includes a compare time and ending at the end of the main trace buffer.Type: GrantFiled: November 25, 2014Date of Patent: March 27, 2018Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Publication number: 20180004574Abstract: Techniques are disclosed for managing lock contention in a multithreaded processing system. In one embodiment, a method includes tracking an amount of time that a lock on a first thread prevents a second thread from execution. The method also includes, if the amount of time is greater than a first threshold, storing the amount of time and an address associated with the lock. The method includes dispatching a third thread that utilizes the address associated with the lock. The method also includes increasing the hardware priority of the third thread during a lock operation.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Mathew ACCAPADI, Grover C. DAVIDSON, II, Dirk MICHEL, Bret R. OLSZEWSKI
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Publication number: 20180004571Abstract: Techniques are disclosed for managing lock contention in a multithreaded processing system. In one embodiment, a method includes tracking a current total amount of time that one or more software threads are prevented from execution due to a lock, a current utilization of one or more hardware threads in the processor, and a current number of dispatchable software threads. If the current total amount of time exceeds a predetermined threshold, the method includes performing a comparison of the current total amount of time, the current utilization, and the current number of dispatchable software threads to one or more past measurements. Based on the comparison, the method includes determining if reducing a number of active hardware threads will reduce a wait time. If reducing the number of active hardware threads will reduce the wait time, reducing the number of active hardware threads.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Mathew ACCAPADI, Grover C. DAVIDSON, II, Dirk MICHEL, Bret R. OLSZEWSKI
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Patent number: 9465807Abstract: A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.Type: GrantFiled: October 18, 2013Date of Patent: October 11, 2016Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 9460101Abstract: A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.Type: GrantFiled: December 5, 2013Date of Patent: October 4, 2016Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Publication number: 20160275024Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.Type: ApplicationFiled: March 20, 2015Publication date: September 22, 2016Inventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Publication number: 20160275025Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.Type: ApplicationFiled: June 11, 2015Publication date: September 22, 2016Inventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 9354934Abstract: Interrupt-intensive and interrupt-driven processes are managed among a plurality of virtual processors, wherein each virtual processor is associated with a physical processor, wherein each physical processor may be associated with a plurality of virtual processors, and wherein each virtual processor is tasked to execute one or more of the processes, by determining which of a plurality of the processes executing among a plurality of virtual processors are being or have been driven by at least a minimum count of interrupts over a period of operational time; selecting a subset of the plurality of virtual processors to form a sequestration pool; migrating the interrupt-intensive processes on to the sequestration pool of virtual processors; and commanding by a computer a bias in delivery or routing of the interrupts to the sequestration pool of virtual processors.Type: GrantFiled: January 5, 2012Date of Patent: May 31, 2016Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover Cleveland Davidson, II, Dirk Michel, Bret Ronald Olszewski
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Publication number: 20160147653Abstract: A method for filtering multiple in-memory trace buffers for event ranges is provided. The method includes allocating a plurality of main trace buffers, based on the number of central processing units (CPU) participating in a trace. Each CPU has a dedicated main trace buffer, and each main trace buffer is circular. Each main trace buffer is divided into an equal number of sub-buffers. A plurality of events is written to the current sub-buffer. When the current sub-buffer is filled, events are written to the next sub-buffer. Events are extracted from at least one of the sub-buffers, starting with the sub-buffer that includes a compare time and ending at the end of the main trace buffer.Type: ApplicationFiled: November 25, 2014Publication date: May 26, 2016Inventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 9195601Abstract: An information handling system (IHS) includes an operating system with a release-behind component that determines which file pages to release from a file cache in system memory. The release-behind component employs a history buffer to determine which file pages to release from the file cache to create room for a current page access. The history buffer stores entries that identify respective pages for which a page fault occurred. For each identified page, the history buffer stores respective repage information that indicates if a repage fault occurred for such page. The release-behind component identifies a candidate previous page for release from the file cache. The release-behind component checks the history buffer to determine if a repage fault occurred for that entry. If so, then the release-behind component does not discard the candidate previous page from the cache. Otherwise, the release-behind component discards the candidate previous page if a repage fault occurred.Type: GrantFiled: November 26, 2012Date of Patent: November 24, 2015Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C Davidson, II, Dirk Michel, Bret R Olszewski
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Patent number: 9038084Abstract: Systems, methods and computer program products may provide managing utilization of one or more physical processors in a shared processor pool. A method of managing utilization of one or more physical processors in a shared processor pool may include determining a current amount of utilization of the one or more physical processors and generating an instruction message. The instruction message may be at least partially determined by the current amount of utilization. The method may further include sending the instruction message to a guest operating system, the guest operating system having a number of enabled virtual processors.Type: GrantFiled: February 23, 2012Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Publication number: 20150113225Abstract: A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.Type: ApplicationFiled: October 18, 2013Publication date: April 23, 2015Applicant: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Publication number: 20150113226Abstract: A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.Type: ApplicationFiled: December 5, 2013Publication date: April 23, 2015Applicant: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 8973007Abstract: According to one aspect of the present disclosure, a method and technique for adaptive lock list searching of waiting threads includes determining an average service time for a lock associated with a shared computing resource; determining an average search time for selecting a thread to next receive the lock from a plurality of threads waiting for the lock; summing the average service time and the average search time; applying a search factor to the summed average service time and average search time to obtain a target search time for searching the waiting threads for selecting the next thread for obtaining the lock; determining a quantity of waiting threads to consider for next obtaining the lock based on the target search time and the average search time, the quantity being less than a total quantity of waiting threads; and identifying the next thread to obtain the lock from the quantity.Type: GrantFiled: December 9, 2013Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 8954974Abstract: A system and technique for adaptive lock list searching of waiting threads includes logic executable by a processor to: determine an average service time for a lock associated with a shared computing resource; determine an average search time for selecting a thread to next receive the lock from a plurality of threads waiting for the lock; sum the average service time and the average search time; apply a search factor to the summed average service time and average search time to obtain a target search time for searching the waiting threads for selecting the next thread for obtaining the lock; determine a quantity of waiting threads to consider for next obtaining the lock based on the target search time and the average search time, the quantity being less than a total quantity of waiting threads; and identify the next thread to obtain the lock from the quantity.Type: GrantFiled: November 10, 2013Date of Patent: February 10, 2015Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 8775749Abstract: Management of a UNIX-style storage pools is enhanced by specially managing one or more memory management inodes associated with pinned and allocated pages of data storage by providing indirect access to the pinned and allocated pages by one or more user processes via a handle, while preventing direct access of the pinned and allocated pages by the user processes without use of the handles; scanning periodically hardware status bits in the inodes to determine which of the pinned and allocated pages have been recently accessed within a pre-determined period of time; requesting via a callback communication to each user process to determine which of the least-recently accessed pinned and allocated pages can be either deallocated or defragmented and compacted; and responsive to receiving one or more page indicators of pages unpinned by the user processes, compacting or deallocating one or more pages corresponding to the page indicators.Type: GrantFiled: June 26, 2013Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Publication number: 20140149672Abstract: An information handling system (IHS) includes an operating system with a release-behind component that determines which file pages to release from a file cache in system memory. The release-behind component employs a history buffer to determine which file pages to release from the file cache to create room for a current page access. The history buffer stores entries that identify respective pages for which a page fault occurred. For each identified page, the history buffer stores respective repage information that indicates if a repage fault occurred for such page. The release-behind component identifies a candidate previous page for release from the file cache. The release-behind component checks the history buffer to determine if a repage fault occurred for that entry. If so, then the release-behind component does not discard the candidate previous page from the cache. Otherwise, the release-behind component discards the candidate previous page if a repage fault occurred.Type: ApplicationFiled: November 26, 2012Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mathew Accapadi, Grover C Davidson, II, Dirk Michel, Bret R Olszewski
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Patent number: 8612986Abstract: A computer program product for scheduling threads in a multiprocessor computer comprises computer program instructions configured to select a thread in a ready queue to be dispatched to a processor and determine whether an interrupt mask flag is set in a thread control block associated with the thread. If the interrupt mask flag is set in the thread control block associated with the thread, the computer program instructions are configured to select a processor, set a current processor priority register of the selected processor to least favored, and dispatch the thread from the ready queue to the selected processor.Type: GrantFiled: June 20, 2012Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Jos M. Accapadi, Mathew Accapadi, Andrew Dunshea, Mark E. Hack, Agustin Mena, III, Mysore S. Srinivas