Patents by Inventor Mathieu Lisart

Mathieu Lisart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10950559
    Abstract: An electronic integrated circuit chip includes a semiconductor substrate with a front side and a back side. A first reflective shield is positioned adjacent the front side of the semiconductor substrate and a second reflective shield is positioned adjacent the back side of the semiconductor substrate. Photons are emitted by a photon source to pass through the semiconductor substrate and bounce off the first and second reflective shields to reach a photon detector at the front side of the semiconductor substrate. The detected photons are processed in order to determine whether to issue an alert indicating the existence of an attack on the electronic integrated circuit chip.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: March 16, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Mathieu Lisart, Bruce Rae
  • Publication number: 20210065834
    Abstract: A method for detecting a writing error of a datum in memory includes: storing at least two parts of equal size of a binary word representative of said datum at the same address in at least two identical memory circuits, and comparing internal control signals of the two memory circuits to determine existence of the writing error.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 4, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice ROMAIN, Mathieu LISART
  • Publication number: 20210067177
    Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 4, 2021
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SAS
    Inventors: Fabrice ROMAIN, Mathieu LISART, Patrick Arnould
  • Patent number: 10861802
    Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: December 8, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart
  • Patent number: 10833027
    Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: November 10, 2020
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Mathieu Lisart, Raul Andres Bianchi, Benoit Froment
  • Patent number: 10754618
    Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 25, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Benoit Froment, Sebastien Petitdidier, Mathieu Lisart, Jean-Marc Voisin
  • Publication number: 20190385957
    Abstract: An electronic integrated circuit chip includes a semiconductor substrate with a front side and a back side. A first reflective shield is positioned adjacent the front side of the semiconductor substrate and a second reflective shield is positioned adjacent the back side of the semiconductor substrate. Photons are emitted by a photon source to pass through the semiconductor substrate and bounce off the first and second reflective shields to reach a photon detector at the front side of the semiconductor substrate. The detected photons are processed in order to determine whether to issue an alert indicating the existence of an attack on the electronic integrated circuit chip.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 19, 2019
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Mathieu LISART, Bruce RAE
  • Patent number: 10497653
    Abstract: A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without reaching the bottom of the well; and a contact with the well formed in each cell.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: December 3, 2019
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Mathieu Lisart, Benoit Froment
  • Publication number: 20190279947
    Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 12, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak MARZAKI, Mathieu LISART
  • Patent number: 10389530
    Abstract: A method for processing content stored on a component is disclosed. A first partition of a first memory is encrypted with a first encryption key and a second partition of the first memory is encrypted with a second encryption key. The second encryption key is different from the first encryption key. The first encryption key is stored in a storage register of the component and the second encryption key is stored in a first location of a non-volatile memory. A memory address of the first location is stored in the first partition of the first memory.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: August 20, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Fabrice Marinet, Mathieu Lisart
  • Patent number: 10389521
    Abstract: A circuit includes a first processing unit and a second identical processing unit. A first communication bus passes encrypted data between one of a plurality of functions and one or both of the first and second processing units. A selection circuit determines whether the encrypted bus is coupled to the first processing unit, the second processing unit, or both of the first and second processing units.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: August 20, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Mathieu Lisart, Benoit Durand, Massimo Cervetto, Christophe Laurencin
  • Publication number: 20190103369
    Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
    Type: Application
    Filed: December 3, 2018
    Publication date: April 4, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian RIVERO, Pascal FORNARA, Guilhem BOUTON, Mathieu LISART
  • Publication number: 20190034168
    Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 31, 2019
    Inventors: Benoit Froment, Sebastien Petitdidier, Mathieu Lisart, Jean-Marc Voisin
  • Patent number: 10186491
    Abstract: An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 22, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: S├ębastien Petitdidier, Mathieu Lisart
  • Patent number: 10177101
    Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: January 8, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart
  • Publication number: 20180277496
    Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.
    Type: Application
    Filed: October 16, 2017
    Publication date: September 27, 2018
    Inventors: Mathieu Lisart, Raul Andres Bianchi, Benoit Froment
  • Patent number: 10079215
    Abstract: An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 18, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Mathieu Lisart, Jimmy Fort
  • Publication number: 20180233460
    Abstract: A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without reaching the bottom of the well; and a contact with the well formed in each cell.
    Type: Application
    Filed: October 19, 2017
    Publication date: August 16, 2018
    Inventors: Mathieu Lisart, Benoit Froment
  • Patent number: 10049982
    Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: August 14, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart
  • Patent number: 10049991
    Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: August 14, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart