Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.

Abstract: A method for processing content stored on a component is disclosed. A first partition of a first memory is encrypted with a first encryption key and a second partition of the first memory is encrypted with a second encryption key. The second encryption key is different from the first encryption key. The first encryption key is stored in a storage register of the component and the second encryption key is stored in a first location of a non-volatile memory. A memory address of the first location is stored in the first partition of the first memory.

Abstract: An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.

Abstract: An integrated circuit including a plurality of first semiconductor strips of a first conductivity type and of second semiconductor strips of a second conductivity type arranged in alternated and contiguous fashion on a region of the second conductivity type, including for each of the first strips: a plurality of bias contacts; for each bias contact, a switch capable of applying a potential on the bias contact; two detection contacts arranged at the ends of the first strip; and a detection circuit having its activation causing the turning off of the switches and the comparison with a threshold of the resistance between the detection contacts.

Abstract: A method for processing content stored on a component is disclosed. A first partition of a first memory is encrypted with a first encryption key and a second partition of the first memory is encrypted with a second encryption key. The second encryption key is different from the first encryption key. The first encryption key is stored in a storage register of the component and the second encryption key is stored in a first location of a non-volatile memory. A memory address of the first location is stored in the first partition of the first memory.

Abstract: An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth.

Abstract: An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth.

Abstract: An integrated circuit including a plurality of first semiconductor strips of a first conductivity type and of second semiconductor strips of a second conductivity type arranged in alternated and contiguous fashion on a region of the second conductivity type, including for each of the first strips: a plurality of bias contacts; for each bias contact, a switch capable of applying a potential on the bias contact; two detection contacts arranged at the ends of the first strip; and a detection circuit having its activation causing the turning off of the switches and the comparison with a threshold of the resistance between the detection contacts.

Abstract: An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth.

Abstract: An integrated circuit including a plurality of first semiconductor strips of a first conductivity type and of second semiconductor strips of a second conductivity type arranged in alternated and contiguous fashion on a region of the second conductivity type, including for each of the first strips: a plurality of bias contacts; for each bias contact, a switch capable of applying a potential on the bias contact; two detection contacts arranged at the ends of the first strip; and a detection circuit having its activation causing the turning off of the switches and the comparison with a threshold of the resistance between the detection contacts.

Abstract: A circuit includes a first processing unit and a second identical processing unit. A first communication bus passes encrypted data between one of a plurality of functions and one or both of the first and second processing units. A selection circuit determines whether the encrypted bus is coupled to the first processing unit, the second processing unit, or both of the first and second processing units.

Abstract: An integrated circuit including a plurality of first semiconductor strips of a first conductivity type and of second semiconductor strips of a second conductivity type arranged in alternated and contiguous fashion on a region of the second conductivity type, including for each of the first strips: a plurality of bias contacts; for each bias contact, a switch capable of applying a potential on the bias contact; two detection contacts arranged at the ends of the first strip; and a detection circuit having its activation causing the turning off of the switches and the comparison with a threshold of the resistance between the detection contacts.

Abstract: A method for processing content stored on a component is disclosed. A first partition of a first memory is encrypted with a first encryption key and a second partition of the first memory is encrypted with a second encryption key. The second encryption key is different from the first encryption key. The first encryption key is stored in a storage register of the component and the second encryption key is stored in a first location of a non-volatile memory. A memory address of the first location is stored in the first partition of the first memory.

Abstract: The component comprises a first memory (MM) comprising a first portion (P1) having a content modified with a first modification entity (K1) and a second portion (P2) having a content modified with a second entity (K2), a storage means (MS) configured to store the first entity (K1) secretly, a non-volatile memory (NVM) storing an item of entity information representative of the second entity (K2) in a location (END) designated by a first indication (INDK2) contained in the said first portion of the first memory.

Abstract: The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit.

Abstract: An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage.

Abstract: An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage.

Abstract: A system for detecting a laser attack on an integrated circuit chip formed in a semiconductor substrate, including a detection device capable of detecting voltage variations of the substrate. The system includes P-type first wells and N-type second wells extending in a P-type upper portion of the substrate; an N-type buried layer extending under at least a portion of the first and second wells; biasing contacts for the second wells and the buried layer; ground contacts for the first wells; and substrate contacts for detecting a substrate voltage, the detection contacts surrounding the first and second wells. The detection device comprises a resistor having a first terminal connected to said ground contacts of the first wells and a second terminal connected to said substrate contacts; and a comparator connected in with the resistor configured to detect a potential difference across the resistor.