Abstract: A diverter valve comprises a valve body defining first (1), second (5) and third (9) inlets and first (3) and second (7) outlets. A passage between the first inlet and the first outlet and first (11) and second (13) interconnected valve members within the valve body, the valve members being jointly movable between first and second positions. In the first position, fluid is able to pass from the first inlet to the second outlet and from the third inlet to the first outlet, the passage between the first inlet and the first outlet being closed. In the second position, fluid is able to pass from the second inlet to the second outlet and along the passage from the first inlet to the first outlet.

Abstract: The present invention relates to the vaporization of liquids and the pressurization of vapors in capillary force vaporizers. More particularly, the invention provides new developments in the assembly and configuration of capillary force vaporizers, as well as systems and methods that incorporate these features, thus providing capillary force vaporizers that exhibit enhanced operability and reliability during operation.

Abstract: The invention provides a compound suitable for use as a catalyst for ring opening polymerisation reactions for example for the polymerisation of lactones, lactides etc, the catalyst comprising the reaction product of (i) an alkoxide, halide, condensed alkoxide, amide, condensed amide, mixed halo-alkoxide or, mixed halo-amide, sulphonic acid derivative, sulphonamide, silanol or silylamide of titanium zirconium, hafnium or aluminium or a mixture thereof, and (ii) a complexing compound selected from the list comprising oximes, hydroxy-Schiff bases, 8-hydroxyquinoline derivatives, 10-hydroxybenzo-[h]-quinoline derivatives, hydrazones and substituted phenols.

Abstract: The throughput of the memory system is improved where error correction of data in a data stream is cryptographically processed with minimal involvement of any controller. To perform error correction when data from the memory cells are read, the bit errors in the data in the data stream passing between the cells and the cryptographic circuit are corrected prior to any cryptographic process performed by the circuit. Preferably the error correction occurs in one or more buffers employed to buffer the data between the cryptographic circuit and the memory where latency is reduced by using multiple buffers.

Abstract: The throughput of the memory system is improved where error correction of data in a data stream is cryptographically processed with minimal involvement of any controller. To perform error correction when data from the memory cells are read, the bit errors in the data in the data stream passing between the cells and the cryptographic circuit are corrected prior to any cryptographic process performed by the circuit. Preferably the error correction occurs in one or more buffers employed to buffer the data between the cryptographic circuit and the memory where latency is reduced by using multiple buffers.