Patents by Inventor Matthew J. King
Matthew J. King has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11322516Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.Type: GrantFiled: August 31, 2020Date of Patent: May 3, 2022Assignee: Micron Technology, Inc.Inventors: Matthew J. King, David A. Daycock, Yoshiaki Fukuzumi, Albert Fayrushin, Richard J. Hill, Chandra S. Tiwari, Jun Fujiki
-
Patent number: 11302710Abstract: Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.Type: GrantFiled: January 10, 2020Date of Patent: April 12, 2022Assignee: Micron Technology, Inc.Inventors: Darwin A. Clampitt, Matthew J. King, John D. Hopkins, M. Jared Barclay
-
Patent number: 11282845Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.Type: GrantFiled: August 24, 2017Date of Patent: March 22, 2022Assignee: Micron Technology, Inc.Inventors: Jun Fang, Fei Wang, Saniya Rathod, Rutuparna Narulkar, Matthew Park, Matthew J. King
-
Publication number: 20220077169Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.Type: ApplicationFiled: November 12, 2021Publication date: March 10, 2022Applicant: Micron Technology, Inc.Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
-
Publication number: 20220077178Abstract: Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of slit structures extends through the stack structure and devices the stack structure into a series of blocks. In a progressed portion of the series of blocks, each block comprises an array of pillars extending the through the stack structure of the block. Also, each block—in the progressed portion—has a different block width than a block width of a neighboring block of the progressed portion of the series of blocks. At least one pillar, of the pillars of the array of pillars in the progressed portion, exhibits bending. Related methods and electronic systems are also disclosed.Type: ApplicationFiled: September 9, 2020Publication date: March 10, 2022Inventors: Kaiming Luo, Sarfraz Qureshi, Md Zakir Ullah, Jessica Low Jing Wen, Harsh Narendrakumar Jain, Kok Siak Tang, Indra V. Chary, Matthew J. King
-
Publication number: 20220068956Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Inventors: Darwin A. Clampitt, Shawn D. Lyonsmith, Matthew J. King, Lisa M. Clampitt, John Hopkins, Kevin Y. Titus, Indra V. Chary, Martin Jared Barclay, Anilkumar Chandolu, Pavithra Natarajan, Roger W. Lindsay
-
Publication number: 20220068955Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Inventors: Matthew J. King, David A. Daycock, Yoshiaki Fukuzumi, Albert Fayrushin, Richard J. Hill, Chandra S. Tiwari, Jun Fujiki
-
Publication number: 20220059566Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Intervening material is formed into the stack laterally-between and longitudinally-along immediately-laterally-adjacent memory block regions. The forming of the intervening material comprises forming pillars laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. The pillars individually extend through multiple of each of the first tiers and the second tiers. After forming the pillars, an intervening opening is formed individually alongside and between immediately-longitudinally-adjacent of the pillars. Fill material is formed in the intervening openings. Other embodiments, including structure, are disclosed.Type: ApplicationFiled: November 2, 2021Publication date: February 24, 2022Applicant: Micron Technology, Inc.Inventor: Matthew J. King
-
Publication number: 20220037350Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.Type: ApplicationFiled: July 30, 2020Publication date: February 3, 2022Inventors: Daniel Billingsley, Matthew J. King, Jordan D. Greenlee, Yongjun J. Hu, Tom George, Amritesh Rai, Sidhartha Gupta, Kyle A. Ritter
-
Publication number: 20210408039Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.Type: ApplicationFiled: September 7, 2021Publication date: December 30, 2021Applicant: Micron Technology, Inc.Inventors: Cole Smith, Ramey M. Abdelrahaman, Silvia Borsari, Chris M. Carlson, David Daycock, Matthew J. King, Jin Lu
-
Publication number: 20210408029Abstract: A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.Type: ApplicationFiled: September 13, 2021Publication date: December 30, 2021Inventors: Matthew J. King, Anilkumar Chandolu, Indra V. Chary, Darwin A. Clampitt, Gordon Haller, Thomas George, Brett D. Lowe, David A. Daycock
-
Patent number: 11205654Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.Type: GrantFiled: August 25, 2019Date of Patent: December 21, 2021Assignee: Micron Technology, Inc.Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
-
Patent number: 11195850Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Intervening material is formed into the stack laterally-between and longitudinally-along immediately-laterally-adjacent memory block regions. The forming of the intervening material comprises forming pillars laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. The pillars individually extend through multiple of each of the first tiers and the second tiers. After forming the pillars, an intervening opening is formed individually alongside and between immediately-longitudinally-adjacent of the pillars. Fill material is formed in the intervening openings. Other embodiments, including structure, are disclosed.Type: GrantFiled: October 18, 2019Date of Patent: December 7, 2021Assignee: Micron Technology, Inc.Inventor: Matthew J. King
-
Publication number: 20210358940Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: May 13, 2020Publication date: November 18, 2021Applicant: Micron Technology, Inc.Inventors: Yiping Wang, Andrew Li, Haoyu Li, Matthew J. King, Wei Yeeng Ng, Yongjun Jeff Hu
-
Patent number: 11177279Abstract: In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.Type: GrantFiled: May 18, 2020Date of Patent: November 16, 2021Assignee: Micron Technology, Inc.Inventors: Matthew J. King, Anilkumar Chandolu, Indra V. Chary, Darwin A. Clampitt, Gordon Haller, Thomas George, Brett D. Lowe, David A. Daycock
-
Publication number: 20210351127Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.Type: ApplicationFiled: July 26, 2021Publication date: November 11, 2021Applicant: Micron Technology, Inc.Inventors: Yi Hu, Harsh Narendrakumar Jain, Matthew J. King
-
Publication number: 20210343624Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.Type: ApplicationFiled: July 6, 2021Publication date: November 4, 2021Applicant: Micron Technology, Inc.Inventors: Indra V. Chary, Chet E. Carter, Anilkumar Chandolu, Justin B. Dorhout, Jun Fang, Matthew J. King, Brett D. Lowe, Matthew Park, Justin D. Shepherdson
-
Patent number: 11152388Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.Type: GrantFiled: October 15, 2019Date of Patent: October 19, 2021Assignee: Micron Technology, Inc.Inventors: Cole Smith, Ramey M. Abdelrahaman, Silvia Borsari, Chris M. Carlson, David Daycock, Matthew J. King, Jin Lu
-
Patent number: 11121146Abstract: A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.Type: GrantFiled: October 15, 2018Date of Patent: September 14, 2021Assignee: Micron Technology, Inc.Inventors: Matthew J. King, Anilkumar Chandolu, Indra V. Chary, Darwin A. Clampitt, Gordon Haller, Thomas George, Brett D. Lowe, David A. Daycock
-
Patent number: 11114379Abstract: A method used in forming integrated circuitry comprises forming a stack of vertically-alternating tiers of different composition materials. A stair-step structure is formed into the stack and an upper landing is formed adjacent and above the stair-step structure. The stair-step structure is formed to comprise vertically-alternating tiers of the different composition materials. A plurality of stairs individually comprise two of the tiers of different composition materials. At least some of the stairs individually have only two tiers that are each only of a different one of the different composition materials. An upper of the stairs that is below the upper landing comprises at least four of the tiers of different composition materials. Structure independent of method is disclosed.Type: GrantFiled: June 1, 2018Date of Patent: September 7, 2021Assignee: Micron Technology, Inc.Inventors: Michael J. Gossman, M. Jared Barclay, Matthew J. King, Eldon Nelson, Matthew Park, Jason Reece, Lifang Xu, Bo Zhao