Patents by Inventor Matthew J. King
Matthew J. King has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11101210Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.Type: GrantFiled: October 25, 2019Date of Patent: August 24, 2021Assignee: Micron Technology, Inc.Inventors: Yi Hu, Harsh Narendrakumar Jain, Matthew J. King
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Publication number: 20210257385Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.Type: ApplicationFiled: March 29, 2021Publication date: August 19, 2021Applicant: Micron Technology, Inc.Inventors: Yi Hu, Merri L. Carlson, Anilkumar Chandolu, Indra V. Chary, David Daycock, Harsh Narendrakumar Jain, Matthew J. King, Jian Li, Brett D. Lowe, Prakash Rau Mokhna Rau, Lifang Xu
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Patent number: 11094592Abstract: A method of forming a semiconductor device comprises forming sacrificial structures and support pillars. The sacrificial structures comprise an isolated sacrificial structure in a slit region and connected sacrificial structures in a pillar region. Tiers are formed over the sacrificial structures and support pillars, and a portion of the tiers are removed to form tier pillars and tier openings, exposing the connected sacrificial structures and support pillars. The connected sacrificial structures are removed to form a cavity, a portion of the cavity extending below the isolated sacrificial structure. A cell film is formed over the tier pillars and over sidewalls of the cavity. A fill material is formed in the tier openings and over the cell film. A portion of the tiers in the slit region is removed, exposing the isolated sacrificial structure, which is removed to form a source opening. The source opening is connected to the cavity and a conductive material is formed in the source opening and in the cavity.Type: GrantFiled: January 22, 2020Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Anilkumar Chandolu, Matthew J. King, Indra V. Chary, Darwin A. Clampitt
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Patent number: 11088017Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.Type: GrantFiled: March 2, 2020Date of Patent: August 10, 2021Assignee: Micron Technology, Inc.Inventors: John B. Matovu, David S. Meyaard, Gowrisankar Damarla, Sri Sai Sivakumar Vegunta, Kunal Shrotri, Shashank Saraf, Kevin R. Gast, Jivaan Kishore Jhothiraman, Suresh Ramarajan, Lifang Xu, Rithu K. Bhonsle, Rutuparna Narulkar, Matthew J. King
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Patent number: 11069598Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.Type: GrantFiled: June 18, 2019Date of Patent: July 20, 2021Assignee: Micron Technology, Inc.Inventors: Indra V. Chary, Chet E. Carter, Anilkumar Chandolu, Justin B. Dorhout, Jun Fang, Matthew J. King, Brett D. Lowe, Matthew Park, Justin D. Shepherdson
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Publication number: 20210217766Abstract: Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.Type: ApplicationFiled: January 10, 2020Publication date: July 15, 2021Applicant: Micron Technology, Inc.Inventors: Darwin A. Clampitt, Matthew J. King, John D. Hopkins, M. Jared Barclay
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Publication number: 20210210499Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, staircase structures within the stack structure and having steps comprising edges of the tiers, and a doped dielectric material adjacent the steps of the staircase structures and comprising silicon dioxide doped with one or more of boron, phosphorus, carbon, and fluorine, the doped dielectric material having a greater ratio of Si—O—Si bonds to water than borophosphosilicate glass. Related methods of forming a microelectronic device and related electronic systems are also disclosed.Type: ApplicationFiled: January 8, 2020Publication date: July 8, 2021Inventors: Jivaan Kishore Jhothiraman, Kunal Shrotri, Matthew J. King
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Publication number: 20210125920Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.Type: ApplicationFiled: October 25, 2019Publication date: April 29, 2021Applicant: Micron Technology, Inc.Inventors: Yi Hu, Harsh Narendrakumar Jain, Matthew J. King
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Publication number: 20210126007Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatus includes a first conductive contact; a second conductive contact; levels of conductive materials stacked over one another and located over the first and second conductive contacts; levels of dielectric materials interleaved with the levels of the conductive materials, the levels of conductive materials and the levels of dielectric materials formed a stack of materials; a first conductive structure located on a first side of the stack of materials and contacting the first conductive contact and a first level of conductive material of the levels of conductive materials; and a second conductive structure located on a second side of the stack of materials and contacting the second conductive contact and a second level of conductive material of the levels of conductive materials.Type: ApplicationFiled: October 25, 2019Publication date: April 29, 2021Inventors: Darwin A. Clampitt, Roger W. Lindsay, Christopher R. Ritchie, Shawn D. Lyonsmith, Matthew J. King, Lisa M. Clampitt
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Publication number: 20210118899Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Intervening material is formed into the stack laterally-between and longitudinally-along immediately-laterally-adjacent memory block regions. The forming of the intervening material comprises forming pillars laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. The pillars individually extend through multiple of each of the first tiers and the second tiers. After forming the pillars, an intervening opening is formed individually alongside and between immediately-longitudinally-adjacent of the pillars. Fill material is formed in the intervening openings. Other embodiments, including structure, are disclosed.Type: ApplicationFiled: October 18, 2019Publication date: April 22, 2021Applicant: Micron Technology, Inc.Inventor: Matthew J. King
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Patent number: 10985179Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.Type: GrantFiled: August 5, 2019Date of Patent: April 20, 2021Assignee: Micron Technology, Inc.Inventors: Yi Hu, Merri L. Carlson, Anilkumar Chandolu, Indra V. Chary, David Daycock, Harsh Narendrakumar Jain, Matthew J. King, Jian Li, Brett D. Lowe, Prakash Rau Mokhna Rau, Lifang Xu
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Publication number: 20210111184Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.Type: ApplicationFiled: October 15, 2019Publication date: April 15, 2021Applicant: Micron Technology, Inc.Inventors: Cole Smith, Ramey M. Abdelrahaman, Silvia Borsari, Chris M. Carlson, David Daycock, Matthew J. King, Jin Lu
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Publication number: 20210057428Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.Type: ApplicationFiled: August 25, 2019Publication date: February 25, 2021Applicant: Micron Technology, Inc.Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
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Publication number: 20210050364Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: August 16, 2019Publication date: February 18, 2021Applicant: Micro Technology, Inc.Inventors: Nicholas R. Tapias, Andrew Li, Adam W. Saxler, Kunal Shrotri, Erik R. Byers, Matthew J. King, Diem Thy N. Tran, Wei Yeeng Ng, Anish A. Khandekar
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Publication number: 20210043644Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.Type: ApplicationFiled: August 5, 2019Publication date: February 11, 2021Applicant: Micron Technology, Inc.Inventors: Yi Hu, Merri L. Carlson, Anilkumar Chandolu, Indra V. Chary, David Daycock, Harsh Narendrakumar Jain, Matthew J. King, Jian Li, Brett D. Lowe, Prakash Rau Mokhna Rau, Lifang Xu
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Publication number: 20200402890Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.Type: ApplicationFiled: June 18, 2019Publication date: December 24, 2020Applicant: Micron Technology, Inc.Inventors: Indra V. Chary, Chet E. Carter, Anilkumar Chandolu, Justin B. Dorhout, Jun Fang, Matthew J. King, Brett D. Lowe, Matthew Park, Justin D. Shepherdson
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Patent number: 10777651Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.Type: GrantFiled: November 27, 2018Date of Patent: September 15, 2020Assignee: Micron Technology, Inc.Inventors: Yushi Hu, John Mark Meldrim, Eric Blomiley, Everett Allen McTeer, Matthew J. King
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Publication number: 20200279867Abstract: In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Inventors: Matthew J. King, Anilkumar Chandolu, Indra V. Chary, Darwin A. Clampitt, Gordon Haller, Thomas George, Brett D. Lowe, David A. Daycock
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Publication number: 20200203220Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.Type: ApplicationFiled: March 2, 2020Publication date: June 25, 2020Inventors: John B. Matovu, David S. Meyaard, Gowrisankar Damarla, Sri Sai Sivakumar Vegunta, Kunal Shrotri, Shashank Saraf, Kevin R. Gast, Jivaan Kishore Jhothiraman, Suresh Ramarajan, Lifang Xu, Rithu K. Bhonsle, Rutuparna Narulkar, Matthew J. King
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Publication number: 20200161187Abstract: A method of forming a semiconductor device comprises forming sacrificial structures and support pillars. The sacrificial structures comprise an isolated sacrificial structure in a slit region and connected sacrificial structures in a pillar region. Tiers are formed over the sacrificial structures and support pillars, and a portion of the tiers are removed to form tier pillars and tier openings, exposing the connected sacrificial structures and support pillars. The connected sacrificial structures are removed to form a cavity, a portion of the cavity extending below the isolated sacrificial structure. A cell film is formed over the tier pillars and over sidewalls of the cavity. A fill material is formed in the tier openings and over the cell film. A portion of the tiers in the slit region is removed, exposing the isolated sacrificial structure, which is removed to form a source opening. The source opening is connected to the cavity and a conductive material is formed in the source opening and in the cavity.Type: ApplicationFiled: January 22, 2020Publication date: May 21, 2020Inventors: Anilkumar Chandolu, Matthew J. King, Indra V. Chary, Darwin A. Clampitt