Patents by Inventor Matthew Metz

Matthew Metz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11017843
    Abstract: In memory devices where a memory cell includes a thin film cell select transistor, selection between layers of such memory cells may further comprise another thin film select transistor. Bitline and wordline encoding suitable for a memory device having a single layer of memory cells may be scaled up to a 3D memory device having two or more memory cell layers. In a DRAM device one layer of (1TFT-1C) cells may include a 2D array of metal-insulator-metal capacitors over an array of TFTs. Additional layers of such 1TFT-1C cells may be stacked monolithically to form a 3D array. Memory cells in each layer may be accessed through a wordline and local bitline. A local bitline of one cell layer may be coupled to global bitline applicable to all cell layers through a layer-selected TFT according to a voltage applied to a layer-select gate voltage.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek Sharma, Gilbert Dewey, Willy Rachmady, Van Le, Matthew Metz, Jack Kavalieros
  • Publication number: 20210031168
    Abstract: An adsorbent bed, including at least one elementary composite structure that includes adsorbent particles in a polymer matrix, wherein the adsorbent bed has a bed packing, ?bed, defined as a volume occupied by the at least one elementary composite structure Vecs divided by a volume of the adsorbent bed Vbed where ?bed is greater than 0.60.
    Type: Application
    Filed: July 11, 2020
    Publication date: February 4, 2021
    Applicants: L'Air Liquide, Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges Claude, Air Liquide Advanced Technologies U.S. LLC
    Inventors: Philippe A. COIGNET, Dean W. KRATZER, Antoine PRUVOT, Matthew METZ
  • Publication number: 20210031135
    Abstract: An adsorbent bed, including at least one elementary composite structure that includes adsorbent particles in a polymer matrix, wherein the adsorbent bed has a bed packing, ?bed, defined as a volume occupied by the at least one elementary composite structure Vecs divided by a volume of the adsorbent bed Vbed where ?bed is greater than 0.60.
    Type: Application
    Filed: July 11, 2020
    Publication date: February 4, 2021
    Applicants: L'Air Liquide, Societe Anonyme pour l'Etude et l?Exploitation des Procedes Georges Claude, Air Liquide Advanced Technologies U.S. LLC
    Inventors: Philippe A. COIGNET, Dean W. KRATZER, Antoine PRUVOT, Federico BRANDANI, Matthew METZ, Elise RENOU
  • Publication number: 20210036023
    Abstract: Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Ashish Agrawal, Jack Kavalieros, Anand Murthy, Gilbert Dewey, Matthew Metz, Willy Rachmady, Cheng-Ying Huang, Cory Bomberger
  • Publication number: 20210008523
    Abstract: An adsorbent bed, including at least one elementary composite structure that includes adsorbent particles in a polymer matrix, wherein the adsorbent bed has a bed packing, ?bed, defined as a volume occupied by the at least one elementary composite structure Vecs divided by a volume of the adsorbent bed Vbed where ?bed is greater than 0.60.
    Type: Application
    Filed: July 11, 2020
    Publication date: January 14, 2021
    Applicants: L'Air Liquide, Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges Claude, Air Liquide Advanced Technologies U.S. LLC
    Inventors: Philippe A. COIGNET, Dean W. KRATZER, Antoine PRUVOT, Matthew METZ
  • Publication number: 20200411669
    Abstract: Embodiments herein describe techniques for a three dimensional transistor above a substrate. A three dimensional transistor includes a channel structure, where the channel structure includes a channel material and has a source area, a drain area, and a channel area between the source area and the drain area. A source electrode is coupled to the source area, a drain electrode is coupled to the drain area, and a gate electrode is around the channel area. An electrode selected from the source electrode, the drain electrode, or the gate electrode is in contact with the channel material on a sidewall of an opening in an inter-level dielectric layer or a surface of the electrode. The electrode is further in contact with the channel structure including the source area, the drain area, or the channel area. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Abhishek SHARMA, Willy RACHMADY, Van H. LE, Jack T. KAVALIEROS, Gilbert DEWEY, Matthew METZ
  • Publication number: 20200411078
    Abstract: In memory devices where a memory cell includes a thin film cell select transistor, selection between layers of such memory cells may further comprise another thin film select transistor. Bitline and wordline encoding suitable for a memory device having a single layer of memory cells may be scaled up to a 3D memory device having two or more memory cell layers. In a DRAM device one layer of (1TFT-1C) cells may include a 2D array of metal-insulator-metal capacitors over an array of TFTs. Additional layers of such 1TFT-1C cells may be stacked monolithically to form a 3D array. Memory cells in each layer may be accessed through a wordline and local bitline. A local bitline of one cell layer may be coupled to global bitline applicable to all cell layers through a layer-selected TFT according to a voltage applied to a layer-select gate voltage.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek Sharma, Gilbert Dewey, Willy Rachmady, Van Le, Matthew Metz, Jack Kavalieros
  • Publication number: 20200403081
    Abstract: Described is a transistor which includes: a source region; a drain region; and a gate region between the source and drain regions, wherein the gate region comprises: high-K dielectric material between spacers such that the high-K dielectric material is recessed; and metal electrode on the recessed high-K dielectric material. The gate recessed gate dielectric allows for using thick gate dielectric even with much advanced process technology nodes (e.g., 7 nm and below).
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Inventors: Seung Hoon Sung, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Matthew Metz, Michael Harper, Jack Kavalieros, Uygar Avci, Ian Young
  • Patent number: 10861939
    Abstract: Semiconductor devices, computing devices, and related methods are disclosed herein. A semiconductor device includes a seed material, an epitaxial material in contact with the seed material, and at least one quantum region including an elastic stiffness that is greater than an elastic stiffness of the epitaxial material. The epitaxial material has lattice parameters that are different from lattice parameters of the seed material by at least a threshold amount. Lattice parameters of the quantum region are within the threshold amount of the lattice parameters of the epitaxial material. A method includes disposing an epitaxial material on a seed material, disposing a quantum region on the epitaxial material, and disposing the epitaxial material on the quantum region.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Matthew Metz, Gilbert Dewey, Harold W. Kennel, Cheng-Ying Huang, Sean T. Ma, Willy Rachmady
  • Publication number: 20200335610
    Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.
    Type: Application
    Filed: February 28, 2018
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Cheng-Ying Huang, Jack Kavalieros, Ian Young, Matthew Metz, Willy Rachmady, Uygar Avci, Ashish Agrawal, Benjamin Chu-Kung
  • Publication number: 20200312976
    Abstract: Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Seung Hoon Sung, Jack Kavalieros, Ian Young, Matthew Metz, Uygar Avci, Devin Merrill, Ashish Verma Penumatcha, Chia-Ching Lin, Owen Loh
  • Publication number: 20200312978
    Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Jack KAVALIEROS, Ian YOUNG, Matthew METZ, Uygar AVCI, Chia-Ching LIN, Owen LOH, Seung Hoon SUNG, Aditya KASUKURTI, Sou-Chi CHANG, Tanay GOSAVI, Ashish Verma PENUMATCHA
  • Patent number: 10784170
    Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau
  • Patent number: 10756198
    Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
  • Publication number: 20200098930
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Van H. LE, Tahi GHANI, Jack T. KAVALIEROS, Gilbert DEWEY, Matthew METZ, Miriam RESHOTKO, Benjamin CHU-KUNG, Shriram SHIVARAMAN, Abhishek SHARMA, NAZILA HARATIPOUR
  • Publication number: 20200098657
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Arnab SEN GUPTA, Matthew METZ, Benjamin CHU-KUNG, Abhishek SHARMA, Van H. LE, Miriam R. RESHOTKO, Christopher J. JEZEWSKI, Ryan ARCH, Ande KITAMURA, Jack T. KAVALIEROS, Seung Hoon SUNG, Lawrence WONG, Tahir GHANI
  • Publication number: 20200098757
    Abstract: An integrated circuit with at least one transistor is formed using a buffer structure on the substrate. The buffer structure includes one or more layers of buffer material and comprises indium, gallium, and phosphorous. A ratio of indium to gallium in the buffer structure increases from a lower value to a higher value such that the buffer structure has small changes in lattice constant to control relaxation and defects. A source and a drain are on top of the buffer structure and a body of Group III-V semiconductor material extends between and connects the source and the drain. A gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Applicant: INTEL CORPORATION
    Inventors: Willy Rachmady, Matthew Metz, Gilbert Dewey, Nicholas Minutillo, Cheng-Ying Huang, Jack Kavalieros, Anand Murthy, Tahir Ghani
  • Publication number: 20200098875
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Seung Hoon SUNG, Justin WEBER, Matthew METZ, Arnab SEN GUPTA, Abhishek SHARMA, Benjamin CHU-KUNG, Gilbert DEWEY, Charles KUO, Nazila HARATIPOUR, Shriram SHIVARAMAN, Van H. LE, Tahir GHANI, Jack T. KAVALIEROS, Sean MA
  • Patent number: 10541305
    Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
  • Publication number: 20200006576
    Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Sean MA, Nicholas MINUTILLO, Cheng-Ying HUANG, Tahir GHANI, Jack KAVALIEROS, Anand MURTHY, Harold KENNEL, Gilbert DEWEY, Matthew METZ, Willy RACHMADY