Patents by Inventor Matthew N. Rocklein
Matthew N. Rocklein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220344451Abstract: Some embodiments include dielectric material having a first region containing HfO and having a second region containing ZrO, where the chemical formulas indicate primary constituents rather than specific stoichiometries. The first region contains substantially no Zr, and the second region contains substantially no Hf. Some embodiments include capacitors having a first electrode, a second electrode, and a dielectric material between the first and second electrodes. The dielectric material includes one or more first regions and one or more second regions. The first region(s) contain(s) Hf and substantially no Zr. The second region(s) contain(s) Zr and substantially no Hf. Some embodiments include memory arrays.Type: ApplicationFiled: April 21, 2021Publication date: October 27, 2022Applicant: Micron Technology, Inc.Inventors: Richard Beeler, Matthew N. Rocklein, Timothy A. Quick, An-Jen B. Cheng, Sumeet C. Pandey
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Patent number: 11417661Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.Type: GrantFiled: March 1, 2020Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
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Publication number: 20220238532Abstract: A DRAM capacitor may include a first capacitor electrode, a capacitor dielectric adjacent to the first capacitor electrode, and a second capacitor electrode adjacent to the capacitor dielectric. The first capacitor electrode may include a lower portion, an upper portion, and a step transition between the lower portion and the upper portion, a width of the upper portion of the first capacitor electrode at the step transition is less than a width of the lower portion of the first capacitor electrode at the step transition. Semiconductor devices, systems, and methods are also disclosed.Type: ApplicationFiled: January 13, 2022Publication date: July 28, 2022Inventors: Devesh Dadhich Shreeram, Kangle Li, Matthew N. Rocklein, Wei Ching Huang, Ping-Cheng Hsu, Sevim Korkmaz, Sanjeev Sapra, An-Jen B. Cheng
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Publication number: 20220208767Abstract: A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.Type: ApplicationFiled: March 17, 2022Publication date: June 30, 2022Inventors: Matthew N. Rocklein, Paul A. Paduano, Sanket S. Kelkar, Christopher W. Petz, Zhe Song, Vassil Antonov, Qian Tao
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Publication number: 20220102630Abstract: Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.Type: ApplicationFiled: December 13, 2021Publication date: March 31, 2022Inventors: Matthew N. Rocklein, D.V. Nirmal Ramaswamy
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Patent number: 11289487Abstract: A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.Type: GrantFiled: February 23, 2018Date of Patent: March 29, 2022Assignee: Micron Technology, Inc.Inventors: Matthew N. Rocklein, Paul A. Paduano, Sanket S. Kelkar, Christopher W. Petz, Zhe Song, Vassil Antonov, Qian Tao
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Patent number: 11251261Abstract: Methods, apparatuses, and systems related to forming a barrier material on an electrode are described. An example method includes forming a top electrode of a storage node on a dielectric material in a semiconductor fabrication sequence and forming, in-situ in a semiconductor fabrication apparatus, a barrier material on the top electrode to reduce damage to the dielectric material when ex-situ of the semiconductor fabrication apparatus.Type: GrantFiled: May 17, 2019Date of Patent: February 15, 2022Assignee: Micron Technology, Inc.Inventors: Sanket S Kelkar, An-Jen B. Cheng, Dojun Kim, Christopher W. Petz, Matthew N. Rocklein, Brenda D. Kraus
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Publication number: 20220028968Abstract: Methods, apparatuses, and systems related to forming a barrier material between an electrode and a dielectric material are described. An example method includes forming a dielectric material on a bottom electrode material of a storage node in a semiconductor fabrication process. The method further includes forming a barrier material on the dielectric material to reduce oxygen vacancies in the dielectric material. The method further includes forming a top electrode on the barrier material.Type: ApplicationFiled: October 11, 2021Publication date: January 27, 2022Inventors: Sanket S. Kelkar, Christopher W. Petz, Dojun Kim, Matthew N. Rocklein, Brenda D. Kraus
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Patent number: 11201286Abstract: Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.Type: GrantFiled: March 9, 2020Date of Patent: December 14, 2021Assignee: Micron Technology, Inc.Inventors: Matthew N. Rocklein, D. V. Nirmal Ramaswamy
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Patent number: 11145710Abstract: Methods, apparatuses, and systems related to forming a barrier material between an electrode and a dielectric material are described. An example method includes forming a dielectric material on a bottom electrode material of a storage node in a semiconductor fabrication process. The method further includes forming a barrier material on the dielectric material to reduce oxygen vacancies in the dielectric material. The method further includes forming a top electrode on the barrier material.Type: GrantFiled: June 26, 2020Date of Patent: October 12, 2021Assignee: Micron Technology, Inc.Inventors: Sanket S. Kelkar, Christopher W. Petz, Dojun Kim, Matthew N. Rocklein, Brenda D. Kraus
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Publication number: 20210313339Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.Type: ApplicationFiled: June 14, 2021Publication date: October 7, 2021Applicant: Micron Technology, Inc.Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, Durai Vishak Nirmal Ramaswamy
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Patent number: 11139256Abstract: Systems, apparatus, and methods related to tamper-resistant integrated circuits are described. The tamper-resistant integrated circuits include tamper-resistant features including a tamper-resistant material formulated or configured to exhibit a change in at least one electrical property responsive to exposure to oxygen, electromagnetic radiation, or other environmental conditions. Data located within the integrated circuit may be erased, or at least a portion of the integrated circuit may be destroyed, responsive to a change in the at least one electrical property. In some examples, one or more electrical properties of a tamper-resistant feature may be measured. A change in an electrical property may be an indication that the associated integrated circuit has been tampered with.Type: GrantFiled: August 21, 2019Date of Patent: October 5, 2021Assignee: Micron Technology, Inc.Inventors: Diana C. Majerus, Scott D. Van De Graaff, Matthew N. Rocklein
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Patent number: 11043502Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.Type: GrantFiled: August 26, 2019Date of Patent: June 22, 2021Assignee: Micron Technology, Inc.Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, Durai Vishak Nirmal Ramaswamy
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Patent number: 10985239Abstract: Methods, apparatuses, and systems related to trim a semiconductor structure using oxygen are described. An example method includes forming a support structure for a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing an electrode material within the opening. The method further includes removing portions of the support structure. The method further includes performing a controlled oxidative trim to an upper portion of the electrode material.Type: GrantFiled: August 16, 2019Date of Patent: April 20, 2021Assignee: Micron Technology, Inc.Inventors: Matthew N. Rocklein, An-Jen B. Cheng, Fredrick D. Fishburn, Sevim Korkmaz, Paul A. Paduano
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Patent number: 10964536Abstract: Methods, apparatuses, and systems related to formation of an atomic layer of germanium (Ge) on a substrate material are described. An example method includes introducing, into a semiconductor processing chamber housing a substrate material having a high aspect ratio, a reducing agent, and introducing, into the semiconductor processing chamber, a germanium amidinate precursor. The example method further includes forming an atomic layer of germanium on the substrate material resulting from a reaction of the reducing agent and the germanium amidinate precursor.Type: GrantFiled: February 6, 2019Date of Patent: March 30, 2021Assignee: Micron Technology, Inc.Inventors: Francois H. Fabreguette, Paul A. Paduano, Gurtej S. Sandhu, John A. Smythe, III, Matthew N. Rocklein
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Publication number: 20210057357Abstract: Systems, apparatus, and methods related to tamper-resistant integrated circuits are described. The tamper-resistant integrated circuits include tamper-resistant features including a tamper-resistant material formulated or configured to exhibit a change in at least one electrical property responsive to exposure to oxygen, electromagnetic radiation, or other environmental conditions. Data located within the integrated circuit may be erased, or at least a portion of the integrated circuit may be destroyed, responsive to a change in the at least one electrical property. In some examples, one or more electrical properties of a tamper-resistant feature may be measured. A change in an electrical property may be an indication that the associated integrated circuit has been tampered with.Type: ApplicationFiled: August 21, 2019Publication date: February 25, 2021Inventors: Diana C. Majerus, Scott D. Van De Graaff, Matthew N. Rocklein
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Publication number: 20210050409Abstract: Methods, apparatuses, and systems related to trim a semiconductor structure using oxygen are described. An example method includes forming a support structure for a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing an electrode material within the opening. The method further includes removing portions of the support structure. The method further includes performing a controlled oxidative trim to an upper portion of the electrode material.Type: ApplicationFiled: August 16, 2019Publication date: February 18, 2021Inventors: Matthew N. Rocklein, An-Jen B. Cheng, Fredrick D. Fishburn, Sevim Korkmaz, Paul A. Paduano
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Publication number: 20210013318Abstract: Apparatuses, methods, and systems related to electrode formation are described. A first portion of a top electrode is formed over a dielectric material of a storage node. A metal oxide is formed over the first portion of the electrode. A second portion of the electrode is formed over the metal oxide.Type: ApplicationFiled: July 11, 2019Publication date: January 14, 2021Inventors: An-Jen B. Cheng, Brenda D. Kraus, Sanket S. Kelkar, Matthew N. Rocklein, Christopher W. Petz, Richard Beeler, Dojun Kim
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Publication number: 20200365684Abstract: Methods, apparatuses, and systems related to forming a barrier material on an electrode are described. An example method includes forming a top electrode of a storage node on a dielectric material in a semiconductor fabrication sequence and forming, in-situ in a semiconductor fabrication apparatus, a barrier material on the top electrode to reduce damage to the dielectric material when ex-situ of the semiconductor fabrication apparatus.Type: ApplicationFiled: May 17, 2019Publication date: November 19, 2020Inventors: Sanket S Kelkar, An-Jen B. Cheng, Dojun Kim, Christopher W. Petz, Matthew N. Rocklein, Brenda D. Kraus
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Patent number: 10811419Abstract: Methods, apparatuses, and systems related to shaping a storage node material are described. An example method includes forming a pillar with a pattern of materials. The method further includes depositing a storage node material on a side of the pillar. The method further includes etching sacrificial materials within the pillar. The method further includes etching the storage node material in a direction from the pillar into the storage node.Type: GrantFiled: May 22, 2019Date of Patent: October 20, 2020Assignee: Micron Technology, Inc.Inventors: Devesh Dadhich Shreeram, Sanket S. Kelkar, Gurpreet S. Lugani, Paul A. Paduano, Matthew N. Rocklein, Sanjeev Sapra, Christopher W. Petz