Patents by Inventor Matthew Purdy

Matthew Purdy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6555397
    Abstract: Various methods of fabricating a conductor structure are provided. In one aspect, a method of fabricating a conductor structure on a first workpiece is provided. A silicon film is formed on the first workpiece. An anti-reflective coating is formed on the silicon film. A mask is formed on a first portion of the anti-reflective coating, while a second portion thereof is left unmasked. The second portion of the anti-reflective coating and the silicon film are etched. The mask is removed, and the anti-reflective coating is removed by isotropic plasma etching. Use of isotropic etching for anti-reflective coating removal eliminates thermal shock associated with heated acid bath anti-reflective coating removal.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: April 29, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Douglas J. Bonser, Matthew Purdy, James H. Hussey, Jr.
  • Patent number: 6409879
    Abstract: A method for controlling spacer width in a semiconductor device is provided. A substrate having a gate formed thereon is provided. An insulative layer is formed over at least a portion of the substrate. The insulative layer covers the gate. The thickness of the insulative layer is measured. A portion of the insulative layer to be removed is determined based on the measured thickness of the insulative layer. The portion of the insulative layer is removed to define a spacer on the gate. A processing line for forming a spacer on a gate disposed on a substrate includes a deposition tool, a thickness metrology tool, and automatic process controller, and a spacer etch tool. The deposition tool is adapted to form an insulative layer over at least a portion of the substrate. The insulative layer covers the gate. The thickness metrology tool is adapted to measure the thickness of the insulative layer.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: June 25, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony J. Toprac, John R. Behnke, Matthew Purdy
  • Patent number: 6365481
    Abstract: Various methods of fabricating a circuit structure, such as a gate electrode or a resistor are provided. In one aspect, a method of fabricating a circuit structure is provided that includes forming a silicon structure on a substrate and forming an oxide film on the silicon structure. A first portion of the oxide film is masked while a second portion is left unmasked. The second portion of the oxide film is removed by isotropic plasma etching to expose a portion of the silicon structure, and the first portion of the oxide film is unmasked. Use of isotropic etching for removal of a resistor protect oxide reduces the potential for isolation structure damage due to aggressive overetching associated with conventional anisotropic etching techniques.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: April 2, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Douglas J. Bonser, Matthew Purdy
  • Patent number: 6245581
    Abstract: The present invention provides for a method and an apparatus for controlling critical dimensions. At least one run of semiconductor devices is processed. A critical dimension measurement is performed upon at least one of the processed semiconductor device. An analysis of the critical dimension measurement is performed. A secondary process upon the semiconductor device in response to the critical dimension analysis is performed.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: June 12, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Douglas Bonser, Anthony J. Toprac, Matthew Purdy, John R. Behnke, James H. Hussey, Jr.
  • Patent number: 6133132
    Abstract: A method for controlling spacer width in a semiconductor device is provided. A substrate having a gate formed thereon is provided. An insulative layer is formed over at least a portion of the substrate. The insulative layer covers the gate. The thickness of the insulative layer is measured. A portion of the insulative layer to be removed is determined based on the measured thickness of the insulative layer. The portion of the insulative layer is removed to define a spacer on the gate. A processing line for forming a spacer on a gate disposed on a substrate includes a deposition tool, a thickness metrology tool, and automatic process controller, and a spacer etch tool. The deposition tool is adapted to form an insulative layer over at least a portion of the substrate. The insulative layer covers the gate. The thickness metrology tool is adapted to measure the thickness of the insulative layer.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: October 17, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony J. Toprac, John R. Behnke, Matthew Purdy