Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Abstract: Disclosed are semiconductor memory devices containing a plastic substrate and at least one active device supported by the plastic substrate, the active device containing an organic semiconductor material. The semiconductor memory devices containing a plastic substrate may further contain a polymer dielectric and/or a conductive polymer.

Abstract: Disclosed are organic semiconductor devices containing a copolymer layer that contains a polymer dielectric and a semiconducting polymer formed using actinic radiation. As initially formed, the copolymer layer has dielectric properties, but portions may selectively rendered conductive after those portions are exposed to actinic radiation. Also disclosed are methods of making the organic semiconductor devices. Such devices are characterized by light weight and robust reliability.

Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Abstract: A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.

Abstract: A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.

Abstract: A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

Abstract: Methods and systems for improving at least one of carrier ion/charge mobility, distribution and permeability in a semiconducting polymer layer of a microelectronic device are disclosed. The methods include forming a semiconducting polymer layer containing at least one semiconducting polymer with one or more ion-complexing side-chain groups. The methods provide for the manufacture of microelectronic devices with one or more of improved carrier ion/charge mobility, distribution and permeability.

Abstract: A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.

Abstract: A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided above the metal material. An intermetallic region can be formed at an interface of the metal material and the barrier layer. The intermetallic material can be formed by implantation of species.

Abstract: A method of forming a conductive structure such as a copper conductive structure, line, or via is optimized for large grain growth and distribution of alloy elements. The alloy elements can reduce electromigration problems associated with the conductive structure. The conductive structure is self-annealed or first annealed in a low temperature process over a longer period of time. Another anneal is utilized to distribute alloy elements.

Abstract: The present invention provides a planar polymer memory device that can operate as a non-volatile memory device. A planar polymer memory device can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and dielectric separate the electrodes. The method for forming a planar polymer memory device comprises at least one of forming a first electrode with an associated plug, forming a second electrode, forming a passive layer over the extension, depositing an organic polymer and patterning the organic polymer. The method affords integration of a planar polymer memory device into a semiconductor fabrication process. A thin film diode (TFD) can further be employed with a planar polymer memory device to facilitate programming. The TFD can be formed between the first electrode and the selectively conductive medium or the second electrode and the selectively conductive medium.

Abstract: A method for manufacturing the memory device by plasma decomposition of sulfur dioxide. A first copper electrode having a surface is provided. The surface of the first copper electrode may be made amorphous. A copper sulfide layer, CuxS, where 1?x?2, is disposed on the copper surface by decomposing sulfur dioxide in an ambient containing excess hydrogen. The copper sulfide layer may be is cuprous sulfide or cupric sulfide. A second copper electrode is coupled to the copper sulfide layer.

Abstract: Disclosed are methods of making memory cells and semiconductor devices containing the memory cells. The methods involve passivating a portion of a copper containing electrode to form a copper sulfide layer in an electrochemical cell by applying a current through a passivation solution containing a sulfide compound. Such devices containing the memory cells are characterized by light weight and robust reliability.

Abstract: A semiconductor device includes source and drain contact regions which include a non-compounded combination of a semiconductor material and at least one metal. The metal may include an elemental metal, such as gold or aluminum, or may include an intermetallic. The contact regions may be formed by depositing a limited amount of the at least one metal on a source and a drain of the device, and annealing the device to induce diffusion of the at least one metal into the source and drain. The annealing time and temperature may be selected to limit diffusion of the at least one metal.

Abstract: A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into an interfacial layer over the barrier material layer, depositing an alloy layer over the interfacial layer. The implanted first alloy element is reactive with the barrier material layer to increase resistance to copper diffusion.

Abstract: The present invention provides a selectively conductive organic semiconductor (e.g., polymer) device that can be utilized as a memory cell. A polymer solution including a conducting polymer self assembles relative to a conductive electrode. The process affords self-assembly such that a shortest conductive path can be achieved. The method includes depositing a concentrated solution of conducting polymer on a conductive surface, applying heat and optionally a vacuum, and permitting the conducting polymer to self-assemble into an organic semiconductor. The organic semiconductor can be employed within single and multi-cell memory devices by forming a structure with two or more electrodes while employing the organic semiconductor along with a passive device between the electrodes. A partitioning component can be integrated with the memory device to facilitate programming and stacking of additional memory cells on top of or in association with previously formed cells.

Abstract: A method of implanting copper barrier material to improve electrical performance in an integrated circuit fabrication process can include providing a copper layer over an integrated circuit substrate, providing a barrier material at a bottom and sides of a via positioned over the copper layer to form a barrier material layer separating the via from the copper layer, implanting a metal species into the barrier material layer, and providing a conductive layer over the via such that the via electrically connects the conductive layer to the copper layer. The implanted metal species can make the barrier material layer more resistant to copper diffusion from the copper layer.