Abstract: A method of forming a MOSFET device is provided including the steps of forming N− lightly doped source and drain extension regions in the top silicon layer, forming spacers above the N− lightly doped source and drain extension regions and forming N+ source and N+ drain regions in the top silicon layer. A silicide film is then provided over the drain and source regions and the spacers are removed. An ion implantation step is then performed to form damaged sidewall regions in the source body and drain body junction.

Abstract: A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

Abstract: A nickel silicide layer is formed on a semiconductor device having a crystalline silicon source/drain region doped with arsenic. Arsenic is doped into the crystalline silicon, by implantation, for example, so that the concentration of arsenic is slightly below the surface of the silicon. Annealing restores the crystalline structure of the silicon after implantation of the arsenic. Amorphous silicon is selectively deposited over the source/drain regions and over the top of the gate electrode. Nickel is deposited over the entire semiconductor device and a second anneal reacts the nickel with the amorphous silicon. The second anneal is timed so that the nickel reacts with the amorphous silicon, and does not substantially react with the silicon source/drain regions containing arsenic. Preventing the nickel from substantially reacting with the silicon source/drain regions containing arsenic provides a smooth interface between the resulting nickel silicide and the silicon source/drain regions doped with arsenic.

Abstract: A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying low temperature silicidation metal to interact to form the self-aligned low temperature metal silicide gate. A precursor having a temporary gate is used to form the self-aligned low temperature silicide gate. The remaining portions of the low temperature silicidation metal is removed by manipulating the etch selectivity between the low temperature silicidation metal and the self-aligned low temperature metal silicide gate.

Abstract: High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are fabricated by forming an ultra-thin catalytic metal layer, e.g., a monolayer thick layer of Pd or Pd, on a Si-based semiconductor substrate, electrolessly plating on the catalytic layer comprising at least one refractory or lanthanum series transition metal or metal-based dielectric precursor layer, such as of Zr and/or Hf, and then reacting the precursor layer with oxygen or with oxygen and the semiconductor substrate to form the at least one high-k metal oxide or silicate.

Abstract: Disadvantageous roughness of interfaces between electrically conductive NiSi layers and n-doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of NMOS transistors and/or CMOS devices is avoided, or at least substantially reduced, by substituting implanted non-As-containing n-type dopant ions, such as P and/or Sb ions, for the conventionally utilized implanted As n-type dopant ions. If desired, shallow-depth source and drain extensions may be formed by implantation of As-containing n-type dopant ions above the region comprising the non-As-containing dopant ions without causing roughness of the NiSi/n-doped Si interface.

Abstract: A damascene gate semiconductor structure that is formed utilizing a silicide stop layer. Initially, a gate opening is provided in an insulating layer on a substrate. A first dielectric layer is deposited in the gate opening over the substrate. A silicide stop layer is then deposited in the gate opening over the first silicon layer. A second silicon layer is then deposited in the gate opening over the silicide stop layer. A metal or alloy layer is then deposited over the insulating and the second silicon layer. The damascene semiconductor structure is then temperature treated to react the metal or alloy layer with the second silicon layer to form a silicide layer. Any unreated metal or alloy is then removed from the metal or alloy layer.

Abstract: An integrated circuit structure includes a planar capacitor positioned adjacent to a logic circuit implemented on a silicon die. The silicon die is bonded to a mounting base using controlled collapse chip connection methods such that a ground terminal of the silicon die is coupled to a ground trace in the mounting base and a Vdd terminal of the silicon die is coupled to a Vdd trace in the mounting base. The capacitor includes via structures with controlled collapse chip connection structures for bonding to the mounting base directly above the silicon die and coupling a first charge accumulation plate to the Vdd trace and a second charge accumulation plate to the ground trace.

Abstract: A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then deposited on the CVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.

Abstract: A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the PVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer.

Abstract: A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. A barrier is then deposited on the CVD amorphous silicon layer. A metal is then formed on the barrier. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer. The work function is preserved by the barrier during subsequent high temperature processing, due to the barrier which prevents interaction between the CVD amorphous silicon layer and the metal, which could otherwise form silicide and change the work function.

Abstract: A silicon on insulator (SOI) device includes an electrically-conducting interface region along a portion of the interface between the insulator and a semiconductor layer atop the insulator. The electrically-conducting interface region provides a “leaky” electrical coupling between the body and source regions of a transistor device such as a “MOSFET”, thereby reducing floating body effects of the device. A method of forming such a semiconductor device includes forming the electrically-conducting interface region by damaging or implanting materials in the insulator and/or the semiconductor in the vicinity of the interface therebetween. The method may include producing a stepped interface region, such as by etching, in order to aid properly locating the transistor device relative to the electrically-conducting interface region.

Abstract: A method of trench isolation includes removal of insulation material after planarization of the insulation material and before stripping of a nitride layer such as polish stop layer. The removal of insulation material may be accomplished, for example, by etching. The amount of material removed may be selected so that a surface of the device is substantially planar after one or more subsequent processing steps.

Abstract: A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.

Abstract: A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the PVD amorphous silicon layer. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer.

Abstract: Nickel salicide processing is implemented by implanting nickel into the active regions, prior to depositing Ni, to catalyze the reaction of Ni and Si during annealing to form a NiSi layer on the polysilicon gate electrodes and source/drain regions without the formation of rough interfaces between the nickel silicide layers and underlying silicon and without conductive bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions, particularly in the presence of silicon nitride sidewall spacers.

Abstract: Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices due to poor compatibility of particular dopants and metal suicides is avoided, or at least substantially reduced, by implanting a first (main) dopant species having relatively good compatibility with the metal silicide, such that the maximum concentration thereof is at a depth above the depth to which silicidation reaction occurs and implanting a second (auxiliary) dopant species having relatively poor compatibility with the metal silicide, wherein the maximum concentration thereof is less than that of the first (main) dopant and is at a depth below the depth to which silicidation reaction occurs. The invention enjoys particular utility in forming NiSi layers on As-doped Si substrates.

Abstract: The present invention relates to a method of manufacturing a silicon-on-insulator semiconductor wafer, including the steps of (1) forming a silicon-on-insulator semiconductor wafer having at least one surface of a monocrystalline silicon film; (2) contacting the at least one surface with phosphorus ions to form a doped region of the monocrystalline silicon film doped with phosphorus above a region of the monocrystalline silicon film which remains undoped; (3) subjecting the wafer to conditions to getter at least one impurity from the undoped region into the doped region; and (4) removing a portion of the monocrystalline silicon film including the doped region from the at least one surface, leaving a substantial portion of the monocrystalline silicon film.

Abstract: A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.

Abstract: A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.