Abstract: A system and method to manage a non-universal encoder and a universal encoder for compression of data include receiving the data. The data includes symbols. The method also includes subdividing the data into a first set of data blocks and a second set of data blocks and generating a non-universal encoder using the first set of data blocks. The non-universal encoder includes first codes. Each of the first codes corresponds to one of the symbols in the first set of data blocks only and at least one of the first codes includes fewer bits than the symbol corresponding to the at least one of the first codes. The method further includes compressing the second set of data blocks using at least the non-universal encoder.

Abstract: A computer system includes a plurality of hardware processors, and a hardware accelerator. A first processor among the plurality of processor runs an application that issues a data compression request to compress or decompress a data stream. The hardware accelerator selectively operates in different modes to compresses or decompresses the data stream. Based on a selected mode, the hardware accelerator can utilize a different number of processors among the plurality of hardware to compress or decompress the data stream.

Abstract: A computer system includes a plurality of hardware processors, and a hardware accelerator. A first processor among the plurality of processor runs an application that issues a data compression request to compress or decompress a data stream. The hardware accelerator selectively operates in different modes to compresses or decompresses the data stream. Based on a selected mode, the hardware accelerator can utilize a different number of processors among the plurality of hardware to compress or decompress the data stream.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.

Abstract: A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: A computer system includes a hardware controller and an internal millicode storage area. The controller includes an accelerator that decompresses a data stream requested by an application. The internal millicode storage area can store a compression dictionary library including a plurality of different pre-defined compression dictionaries. A host system includes a dictionary manager that determines a compression dictionary from the plurality of different pre-defined compression dictionaries included in the dictionary library to decompress the data stream. The accelerator can access the internal millicode storage area to obtain the determined compression dictionary, and to decompress the data stream according to the determined compression dictionary.

Abstract: An aspect includes hardware accelerator access. An application executing on a core of a multi-core processor triggers an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores. The interface code routine partitions an input work package of the application into a plurality of pages in one or more input queues. The input work package is provided to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator.

Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.

Abstract: Various embodiments are disclosed that relate to electronic display of serially presented text using techniques for placement of an optimal recognition position of words at a fixed display location. In some embodiments, the optimal recognition position is based on empirically determined optimal recognition positions. In some embodiments, an optimal recognition position character is displayed at the fixed display location. In other embodiments, an optimal recognition proportionate position is displayed at the fixed display location. Various related techniques for processing and displaying text are further disclosed herein.

Abstract: A computer system includes a hardware controller and an internal millicode storage area. The controller includes an accelerator that decompresses a data stream requested by an application. The internal millicode storage area can store a compression dictionary library including a plurality of different pre-defined compression dictionaries. A host system includes a dictionary manager that determines a compression dictionary from the plurality of different pre-defined compression dictionaries included in the dictionary library to decompress the data stream. The accelerator can access the internal millicode storage area to obtain the determined compression dictionary, and to decompress the data stream according to the determined compression dictionary.

Abstract: Systems, methods, and computer-readable media are described for performing data compression in a manner that does not require software to make a call to hardware to close a compressed data block, thereby reducing computational overhead. In response to a request from software to data compression hardware for a data encoding, the hardware may return the data encoding as well as an end-of-block symbol encoding value and bit length. The hardware may load the end-of-block symbol encoding value and bit length into a different area in the returned structure such that the software has direct access to the value. When the software determines that a block should be closed, the software may retrieve the end-of-block symbol and insert it into the block without needing to make a call to hardware. The software may then make a call to the hardware to request a new data encoding for subsequent compressed data blocks.

Abstract: A computer system includes a plurality of hardware processors, and a hardware accelerator. A first processor among the plurality of processor runs an application that issues a data compression request to compress or decompress a data stream. The hardware accelerator selectively operates in different modes to compresses or decompresses the data stream. Based on a selected mode, the hardware accelerator can utilize a different number of processors among the plurality of hardware to compress or decompress the data stream.

Abstract: A computer system includes a hardware controller and a host system. The hardware controller includes an accelerator to encode a data stream requested by an application based on a version of the accelerator. The host system executes a compression library linked to the application. The compression library operates according to one or more behavior characteristics to execute a compression algorithm that compresses the encoded data provided by the hardware controller. The behavior characteristics of the compression library is actively changed based on the version of the accelerator.

Abstract: An aspect includes hardware accelerator access. An application executing on a core of a multi-core processor triggers an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores. The interface code routine partitions an input work package of the application into a plurality of pages in one or more input queues. The input work package is provided to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator. An output work package is provided from the hardware accelerator in groups of one or more pages to the application.

Abstract: A method for coupling transactions with a configurable ordering controller in a computer system. The method comprises sending, by a coupling device, first data packets with an unordered attribute being set to an ordering controller. The method further comprises sending, by the coupling device, second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The method further comprises sending, by the ordering controller, the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.

Abstract: Embodiments include methods, systems and computer program products method for maintaining ordered memory access with parallel access data streams associated with a distributed shared memory system. The computer-implemented method includes performing, by a first cache, a key check, the key check being associated with a first ordered data store. A first memory node signals that the first memory node is ready to begin pipelining of a second ordered data store into the first memory node to an input/output (I/O) controller. A second cache returns a key response to the first cache indicating that the pipelining of the second ordered data store can proceed. The first memory node sends a ready signal indicating that the first memory node is ready to continue pipelining of the second ordered data store into the first memory node to the I/O controller, wherein the ready signal is triggered by receipt of the key response.

Abstract: A computer system includes a host system that runs an application. The application outputs a compression request to compress a data stream having an initial data-representation size, and which includes a plurality of individual data chunks. A hardware controller compresses the plurality of individual data chunks according to different encodings based on a compression ratio of each of the individual data chunks to generate a compressed data stream having a reduced data-representation size with respect to the initial data-representation size.