Abstract: A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system is configured to purge a device table cache (DTC) in response to the processor executing the program instructions. An operating system runs on the synchronous I/O computing system and issues a synchronous I/O command indicating a request to perform a device table entry transaction that has a total data length to be transferred. A device table entry is selected from a device table, loaded into the DTC, and data packets corresponding to the device table entry transaction are transferred using the selected device table entry. A host bridge processor monitors the data packets transferred using the selected table entry, and automatically purges the selected device table entry from the DTC in response to determining the transferred data packets match the total data length.

Abstract: An aspect includes hardware accelerator access. An application executing on a core of a multi-core processor triggers an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores. The interface code routine partitions an input work package of the application into a plurality of pages in one or more input queues. The input work package is provided to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator. An output work package is provided from the hardware accelerator in groups of one or more pages to the application.

Abstract: A computer system with a configurable ordering controller for coupling transactions. The computer system comprises a coupling device configured to send first data packets with an unordered attribute being set to an ordering controller. The computer system further comprises the coupling device configured to send second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The computer system further comprises the ordering controller configured to send the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

Abstract: Systems, methods, and computer-readable media are described for performing data compression in a manner that does not require software to make a call to hardware to close a compressed data block, thereby reducing computational overhead. In response to a request from software to data compression hardware for a data encoding, the hardware may return the data encoding as well as an end-of-block symbol encoding value and bit length. The hardware may load the end-of-block symbol encoding value and bit length into a different area in the returned structure such that the software has direct access to the value. When the software determines that a block should be closed, the software may retrieve the end-of-block symbol and insert it into the block without needing to make a call to hardware. The software may then make a call to the hardware to request a new data encoding for subsequent compressed data blocks.

Abstract: A system and method to manage a non-universal encoder and a universal encoder for compression of data include receiving the data. The data includes symbols. The method also includes subdividing the data into a first set of data blocks and a second set of data blocks and generating a non-universal encoder using the first set of data blocks. The non-universal encoder includes first codes. Each of the first codes corresponds to one of the symbols in the first set of data blocks only and at least one of the first codes includes fewer bits than the symbol corresponding to the at least one of the first codes. The method further includes compressing the second set of data blocks using at least the non-universal encoder.

Abstract: A compare unit includes an array including a plurality of buffer pairs to receive records on one level of a plurality of levels of a hierarchical structure. A comparator is coupled to the array, and the comparator includes one input to receive one beat of one record from one buffer of a selected buffer pair of the plurality of buffer pairs coupled to the comparator. The comparator further includes another input to receive another beat of another record from another buffer of the selected buffer pair, and logic coupled to the one input and the other input to compare the one beat and the other beat to obtain a winner beat of the compare.

Abstract: A logic device includes a compare unit at one level of a plurality of levels of a hierarchical structure to be used in sorting of records. The compare unit includes a buffer pair in which one or more buffers of the buffer pair are adapted to store at least one record. The logic device further includes another compare unit on another level of the plurality of levels of the hierarchical structure. The other compare unit includes another buffer pair in which one or more other buffers of the other buffer pair are adapted to store a portion of a record. A size of the one or more other buffers of the other buffer pair is insufficient to store the entire record. The one compare unit and the other compare unit are adapted to sort a plurality of records.

Abstract: A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system purges one or more address translation entries in response to the processor executing the program instructions to issue, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction. The program instructions further command the operating system to select a device table entry from a device table, load the entry into the DTC, request required address translation entries, install the required address translation entries in the address translation cache, and transfer data packets corresponding to the transaction. The program instructions further command the operating system to automatically purge the address translation cache entries associated with a transaction in response to detect that the transaction is completed.

Abstract: A computer-implemented method for computer-implemented method for communicating completion of synchronous input/output (I/O) commands between a processor executing an operating system and a recipient control unit is described. The method may include issuing, by a processor, a Synchronous I/O command to the recipient control unit; receiving, with the processor, a DMA read request from the recipient control unit; converting, with the processor, the DMA read response to write a data record into memory of the recipient control unit; issuing the DMA read request to the recipient control unit, wherein the DMA read request comprises an echo read portion comprising at least one byte of information at the end of the data record written; receiving, by the processor, a DMA write confirmation comprising the echo read portion of the record; and writing the echo read portion to a status area.

Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.

Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.

Abstract: A computing system includes a processor and a memory unit that stores program instructions. The system purges an entry from an address translation cache in response to the processor executing the program instructions to perform issuing, via an operating system running on the computing system, a command indicating a request to perform an I/O transaction requiring a translation entry. A host bridge monitors a total data length of the address translation entry to be transferred during the I/O transaction. An address translation entry is selected from an address translation table, loaded into the address translation cache, and data corresponding to the I/O transaction is transferred using the selected address translation entry. The host bridge automatically purges the selected address translation entry from the address translation cache in response to determining the transferred amount of data matches the total data length for the address translation entry.

Abstract: Embodiments include methods, systems, and computer program products for performing synchronous data I/O. Aspects include a processor of computer system sending a store block to request data from a device through a PCIe connection, requested data having a predetermined number of data blocks, and the processor executing a data transaction loop to retrieve requested data. Executing the data transaction loop may include writing to a table prefetch trigger register on host bridge to queue up speculative prefetches in ETU for each data block. The host bridge may perform a first speculative prefetch to install a device table entry in a device table cache. The processor may further perform a second speculative prefetch to install an address translation in an address translation cache. The host bridge processes the data block received through direct memory access over the PCIe connection using the prefetched device table entry and address translation.

Abstract: A method for coupling transactions with a configurable ordering controller in a computer system. The method comprises sending, by a coupling device, first data packets with an unordered attribute being set to an ordering controller. The method further comprises sending, by the coupling device, second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The method further comprises sending, by the ordering controller, the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

Abstract: Embodiments include methods, systems and computer program products method for maintaining ordered memory access with parallel access data streams associated with a distributed shared memory system. The computer-implemented method includes performing, by a first cache, a key check, the key check being associated with a first ordered data store. A first memory node signals that the first memory node is ready to begin pipelining of a second ordered data store into the first memory node to an input/output (I/O) controller. A second cache returns a key response to the first cache indicating that the pipelining of the second ordered data store can proceed. The first memory node sends a ready signal indicating that the first memory node is ready to continue pipelining of the second ordered data store into the first memory node to the I/O controller, wherein the ready signal is triggered by receipt of the key response.

Abstract: A computer system with a configurable ordering controller for coupling transactions. The computer system comprises a coupling device configured to send first data packets with an unordered attribute being set to an ordering controller. The computer system further comprises the coupling device configured to send second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The computer system further comprises the ordering controller configured to send the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

Abstract: A data processing apparatus is provided, which includes: a plurality of processor cores; a shared processor cache, the shared processor cache being connected to each of the processor cores and to a main memory; a bus controller, the bus controller being connected to the shared processor cache and performing, in response to receiving a descriptor sent by one of the processor cores, a transfer of requested data indicated by the descriptor from the shared processor cache to an input/output (I/O) device; a bus unit, the bus unit being connected to the bus controller and transferring data to/from the I/O device; wherein the shared processor cache includes means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access in response to receiving a descriptor from the one of the processor cores.

Abstract: A computing system includes a processor and a memory unit that stores program instructions. The system purges an entry from an address translation cache in response to the processor executing the program instructions to perform issuing, via an operating system running on the computing system, a command indicating a request to perform an I/O transaction requiring a translation entry. A host bridge monitors a total data length of the address translation entry to be transferred during the I/O transaction. An address translation entry is selected from an address translation table, loaded into the address translation cache, and data corresponding to the I/O transaction is transferred using the selected address translation entry. The host bridge automatically purges the selected address translation entry from the address translation cache in response to determining the transferred amount of data matches the total data length for the address translation entry.

Abstract: A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.