Abstract: In a metallization system of a sophisticated semiconductor device, metal pillars may be provided so as to exhibit an increased efficiency in distributing any mechanical stress exerted thereon. This may be accomplished by significantly increasing the surface area of the final passivation layer that is in tight mechanical contact with the metal pillar.

Abstract: A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.

Abstract: In a reflow process for connecting a semiconductor die and a package substrate, the temperature gradient and thus the thermally induced mechanical forces in a sensitive metallization system of the semiconductor die may be reduced during the cooling phase. To this end, one or more heating intervals may be introduced into the cooling phase, thereby efficiently reducing the temperature difference. In other cases, the central region may additionally be cooled by providing appropriate locally restricted mechanisms, such as a locally restricted gas flow and the like. Consequently, desired short overall process times may be obtain without contributing to increased yield losses when processing sophisticated metallization systems on the basis of a lead-free contact regime.

Abstract: The metallization system of complex semiconductor devices may be evaluated in terms of mechanical integrity on the basis of a measurement system and measurement procedures in which individual contact elements, such as metal pillars or solder bumps, are mechanically stimulated, while the response of the metallization system, for instance in the form of directly measured forces, is determined in order to quantitatively evaluate mechanical status of the metallization system. In this manner, the complex material systems and the mutual interactions thereof may be efficiently assessed.

Abstract: By dividing a single chip area into individual sub-areas, a thermally induced stress in each of the sub-areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip may be used compared to conventional strategies.

Abstract: A system and method for creating extension fields for business objects are described. In various embodiments, a system includes modules to display business processes and business objects thereof in graphical user interface screens. In various embodiments, the system propagates created extension fields to other business objects via metadata derived from selections in the graphical user interface. In various embodiments, a method for propagating extension fields from one business object to another business object via a data flow between the two business objects is presented. In various embodiments, the method receives instructions from a graphical user interface for the propagation of an extension field and sends instructions to a backend module to propagate the extension field from the source business object to the other business object.

Abstract: By introducing a metallic species into an exposed surface area of a copper region, the electromigration behavior of this surface area may be significantly enhanced. The incorporation of the metallic species may be accomplished in a highly selective manner so as to not unduly affect dielectric material positioned adjacent to the metal region, thereby essentially avoiding undue increase of leakage currents.

Abstract: A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 ?m may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region.

Abstract: By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified.

Abstract: By providing a barrier layer stack including a thin SiCN layer for enhanced adhesion, a silicon nitride layer for confining a copper-based metal region (thereby also effectively avoiding any diffusion of oxygen and moisture into the copper region), and a SiCN layer, the total relative permittivity may still be maintained at a low level, since the thickness of the first SiCN layer and of the silicon nitride layer may be moderately thin, while the relatively thick silicon carbide nitride layer provides the required high etch selectivity during a subsequent patterning process of the low-k dielectric layer.

Abstract: A technique is provided that enables the formation of metal silicide individually for N-channel transistors and P-channel transistors, while at the same time a strain-inducing mechanism is also provided individually for each transistor type. In this way, a cobalt silicide having a reduced distance to the channel region of an NMOS transistor may be provided, while a P-channel transistor may receive a highly conductive nickel silicide, without unduly affecting or compromising the characteristics of the N-channel transistor.

Abstract: By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified.

Abstract: By forming a large metal pad and removing any excess material thereof, a pronounced recessed surface topography may be obtained, which may also affect the further formation of a metallization layer of a semiconductor device, thereby increasing the probability of maintaining metal residues above the recessed surface topography. Consequently, by providing test metal lines in the area of the recessed surface topography, the performance of a respective CMP process may be estimated with increased efficiency.

Abstract: A test structure or a circuit element acting temporarily as a test structure may be provided within the die region of sophisticated semiconductor devices, while probe pads may be located in the frame in order to not unduly consume valuable die area. The electrical connection between the test structure and the probe pads may be established by a conductive path including a buried portion, which extends from the die region into the frame below a die seal, thereby maintaining the electrical and mechanical characteristics of the die seal. Hence, enhanced availability of electrical measurement data and superior authenticity of the data may be accomplished, wherein the measurement data may be obtained during the production process.

Abstract: The present invention relates to novel heteroaryl-substituted acetone derivatives inhibiting the enzyme phospholipase A2, and pharmaceutical agents comprising said compounds.

Abstract: In sophisticated semiconductor devices, a chip-package interconnect structure may be established on the basis of a metal pillar without using a solder bump material in the package. In this case, the complexity of the manufacturing process for forming the wiring system of the package may be significantly reduced, while also providing the possibility of increasing packing density of the pillar structure.

Abstract: A vertical or three-dimensional non-planar configuration for a decoupling capacitor is provided, which significantly reduces the required die area for capacitors of high charge carrier storage capacity. The non-planar configuration of the decoupling capacitors also provides enhanced pattern uniformity during the highly critical gate patterning process.

Abstract: In complex metallization systems of sophisticated semiconductor devices, appropriate stress compensation mechanisms may be implemented in order to reduce undue substrate deformation during the overall manufacturing process. For example, additional dielectric material and/or functional layers of one or more metallization layers may be provided with appropriate internal stress levels so as to maintain substrate warpage at a non-critical level, thereby substantially reducing yield losses in the manufacturing process caused by non-reliable attachment of substrates to substrate holders in process and transport tools.

Abstract: In a metallization system of a sophisticated semiconductor device, metal pillars may be provided so as to exhibit an increased efficiency in distributing any mechanical stress exerted thereon. This may be accomplished by significantly increasing the surface area of the final passivation layer that is in tight mechanical contact with the metal pillar.

Abstract: In a semiconductor device, electrical measurement data may be obtained with enhanced spatial resolution, for instance from within the entire die region, by providing a distributed sensor structure, each of which may be individually accessed by an appropriate interconnect structure, while nevertheless maintaining the required number of terminals and test signals at a low level.