Patents by Inventor Maw-Song Chen

Maw-Song Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10600812
    Abstract: A manufacturing method of an array substrate including following steps is provided. A plurality of scan lines are formed on a substrate having a pixel region and a fan-out region. A plurality of data lines are formed. A plurality of transistors are formed and respectively electrically connected to the corresponding scan lines and data lines. A plurality of common electrodes are formed. A plurality of pixel electrodes are formed and respectively electrically connected to the corresponding transistors. A plurality of first fan-out lines, second fan-out lines, and third fan-out lines are formed in the fan-out region. Each of the third fan-out lines includes a transparent conductive layer and an auxiliary conductive layer located on and contacting the transparent conductive layer. The third fan-out lines and the common electrodes are formed by the same photomask.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: March 24, 2020
    Assignee: Au Optronics Corporation
    Inventors: Wen-Yi Hsu, Pei-Ming Chen, Maw-Song Chen
  • Publication number: 20190386032
    Abstract: A manufacturing method of an array substrate including following steps is provided. A plurality of scan lines are formed on a substrate having a pixel region and a fan-out region. A plurality of data lines are formed. A plurality of transistors are formed and respectively electrically connected to the corresponding scan lines and data lines. A plurality of common electrodes are formed. A plurality of pixel electrodes are formed and respectively electrically connected to the corresponding transistors. A plurality of first fan-out lines, second fan-out lines, and third fan-out lines are formed in the fan-out region. Each of the third fan-out lines includes a transparent conductive layer and an auxiliary conductive layer located on and contacting the transparent conductive layer. The third fan-out lines and the common electrodes are formed by the same photomask.
    Type: Application
    Filed: January 15, 2019
    Publication date: December 19, 2019
    Applicant: Au Optronics Corporation
    Inventors: Wen-Yi Hsu, Pei-Ming Chen, Maw-Song Chen
  • Patent number: 10121901
    Abstract: A pixel structure including an active device, a first protection layer, a first electrode, an isolator, a second protection layer and a second electrode is provided. The active device includes a gate, a source and a drain. The first protection layer covers the active device and has a first opening above the drain. The first electrode is disposed above the first protection layer. The first electrode has a side wall corresponding to the first opening. The isolator covers the side wall of the first electrode. The second protection layer covers the first electrode. The second electrode is disposed on the second protection layer, electrically connected to the drain through the first opening, and electrically isolated from the first electrode by the second protection layer and the isolator.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: November 6, 2018
    Assignee: Au Optronics Corporation
    Inventors: Fu-Chun Tsao, Kuo-Yu Huang, Maw-Song Chen
  • Patent number: 9581867
    Abstract: A display panel including first and second pixel structures and a light shielding pattern layer is provided. The first pixel structure includes a first pixel electrode including first pixel electrode bars, wherein a first maximum spacing is formed between any two adjacent first pixel electrode bars of the first pixel structure. The second pixel structure includes a second pixel electrode including second pixel electrode bars, wherein a second maximum spacing which is larger than the first maximum spacing is formed between two adjacent second pixel electrode bars of the second pixel structure. The light shielding pattern layer has first and second light shielding portions. The area of the second light shielding portion is larger than the area of the first light shielding portion. The first pixel electrode is close to the second light shielding portion and the second pixel electrode is away from the second light shielding portion.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: February 28, 2017
    Assignee: Au Optronics Corporation
    Inventors: Zheng-Han Li, Kuo-Yu Huang, Ruei-Pei Chen, Maw-Song Chen
  • Patent number: 9581871
    Abstract: A display panel, including a device substrate, an opposite substrate, a sealant, and a display medium, is provided. A pixel array of the device substrate is located in a display region, and a periphery circuit of the device substrate is located in a non-display region, wherein the periphery circuit includes at least one driving device, a planarization layer, and at least one wire. The planarization layer covers the driving device. The wire is located on the planarization layer, and the wire is electrically connected with the driving device and disposed to overlap the driving device. The opposite substrate is located opposite to the device substrate, and the sealant is located in the non-display region therebetween and covers the wire. The display medium is located between the device substrate, the opposite substrate, and the sealant. A manufacturing method of a display panel is also provided.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: February 28, 2017
    Assignee: Au Optronics Corporation
    Inventors: Wen-Yi Hsu, Maw-Song Chen
  • Publication number: 20170033235
    Abstract: A pixel structure including an active device, a first protection layer, a first electrode, an isolator, a second protection layer and a second electrode is provided. The active device includes a gate, a source and a drain. The first protection layer covers the active device and has a first opening above the drain. The first electrode is disposed above the first protection layer. The first electrode has a side wall corresponding to the first opening. The isolator covers the side wall of the first electrode. The second protection layer covers the first electrode. The second electrode is disposed on the second protection layer, electrically connected to the drain through the first opening, and electrically isolated from the first electrode by the second protection layer and the isolator.
    Type: Application
    Filed: July 22, 2016
    Publication date: February 2, 2017
    Applicant: Au Optronics Corporation
    Inventors: Fu-Chun Tsao, Kuo-Yu Huang, Maw-Song Chen
  • Patent number: 9423660
    Abstract: A display panel is provided. The display panel has a display area and a peripheral area and includes a plurality of pixels, a plurality of data lines and a plurality of signal traces. The pixels are disposed on the display area and arranged in an array. The data lines extend from the display area to the peripheral area and are respectively electrically connected to a plurality of columns of pixel. The signal traces extend from the display area to the peripheral area and are parallel to the data lines. In addition, the data lines and the signal traces are respectively disposed between two columns of pixels, and the signal traces include a plurality of gate signal traces.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: August 23, 2016
    Assignee: Au Optronics Corporation
    Inventors: Te-Chun Huang, Kuo-Yu Huang, Yu-Han Huang, Maw-Song Chen, Wei-Ming Huang
  • Publication number: 20160155752
    Abstract: A display panel is provided. The display panel has a display area and a peripheral area and includes a plurality of pixels, a plurality of data lines and a plurality of signal traces. The pixels are disposed on the display area and arranged in an array. The data lines extend from the display area to the peripheral area and are respectively electrically connected to a plurality of columns of pixel. The signal traces extend from the display area to the peripheral area and are parallel to the data lines. In addition, the data lines and the signal traces are respectively disposed between two columns of pixels, and the signal traces include a plurality of gate signal traces.
    Type: Application
    Filed: March 9, 2015
    Publication date: June 2, 2016
    Inventors: Te-Chun Huang, Kuo-Yu Huang, Yu-Han Huang, Maw-Song Chen, Wei-Ming Huang
  • Patent number: 9356208
    Abstract: A manufacturing method of pixel structure includes forming a first conductive layer on a substrate and forming a first insulation layer thereon; forming a second conductive layer on the first insulation layer; forming a second insulation layer on the second conductive layer; forming a semiconductor layer on the second insulation layer above the gate; forming a third conductive layer on the second insulation layer, wherein the gate, the semiconductor layer, the source, and the drain together constitute a thin film transistor, and the first electrode, the second electrode, and the third electrode together constitute a capacitor; forming a third insulation layer on the third conductive layer; and forming a pixel electrode on the third insulation layer, the pixel electrode being electrically connected to the drain.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: May 31, 2016
    Assignee: Au Optronics Corporation
    Inventors: Chuan-Sheng Wei, Chau-Shiang Huang, Wu-Liu Tsai, Chih-Hung Lin, Maw-Song Chen
  • Publication number: 20160043104
    Abstract: A display panel including first and second pixel structures and a light shielding pattern layer is provided. The first pixel structure includes a first pixel electrode including first pixel electrode bars, wherein a first maximum spacing is formed between any two adjacent first pixel electrode bars of the first pixel structure. The second pixel structure includes a second pixel electrode including second pixel electrode bars, wherein a second maximum spacing which is larger than the first maximum spacing is formed between two adjacent second pixel electrode bars of the second pixel structure. The light shielding pattern layer has first and second light shielding portions. The area of the second light shielding portion is larger than the area of the first light shielding portion. The first pixel electrode is close to the second light shielding portion and the second pixel electrode is away from the second light shielding portion.
    Type: Application
    Filed: October 23, 2014
    Publication date: February 11, 2016
    Inventors: Zheng-Han Li, Kuo-Yu Huang, Ruei-Pei Chen, Maw-Song Chen
  • Publication number: 20150263050
    Abstract: A pixel structure includes a gate electrode, a gate dielectric layer, a silicon channel layer, a silicon source ohmic contact layer, a silicon drain ohmic contact layer, a source auxiliary ohmic contact layer, a drain auxiliary ohmic contact layer, a transparent conductive portion, a transparent pixel electrode, a source electrode, and a drain electrode. The silicon channel layer is disposed on the gate dielectric layer and above the gate electrode. The silicon source ohmic contact layer, the source auxiliary ohmic contact layer, the transparent conductive portion, and the source electrode are disposed on the silicon channel layer in sequence. The silicon drain ohmic contact layer and the drain auxiliary ohmic contact layer are disposed on the silicon channel layer in sequence. At least a portion of the transparent pixel electrode is disposed between the drain electrode and the drain auxiliary ohmic contact layer.
    Type: Application
    Filed: May 14, 2014
    Publication date: September 17, 2015
    Applicant: AU Optronics Corporation
    Inventors: Wen-Yi HSU, Maw-Song CHEN, Kuo-Yu HUANG
  • Publication number: 20140340625
    Abstract: A display panel, including a device substrate, an opposite substrate, a sealant, and a display medium, is provided. A pixel array of the device substrate is located in a display region, and a periphery circuit of the device substrate is located in a non-display region, wherein the periphery circuit includes at least one driving device, a planarization layer, and at least one wire. The planarization layer covers the driving device. The wire is located on the planarization layer, and the wire is electrically connected with the driving device and disposed to overlap the driving device. The opposite substrate is located opposite to the device substrate, and the sealant is located in the non-display region therebetween and covers the wire. The display medium is located between the device substrate, the opposite substrate, and the sealant. A manufacturing method of a display panel is also provided.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 20, 2014
    Applicant: Au Optronics Corporation
    Inventors: Wen-Yi Hsu, Maw-Song Chen
  • Patent number: 8786815
    Abstract: A display panel having a display region and a non-display region is provided. The display panel includes a plurality of pixel structures in the display region, and each pixel structure includes a scan line, a data line, a first active device, a pixel electrode, a first insulating layer, a capacitor electrode, and a second insulating layer. The first active device includes a first gate, a first channel, a first source, and a first drain. The second insulating layer covers the first insulating layer and the capacitor electrode and is located between the capacitor electrode and the first drain. At least one driving circuit is disposed in the non-display region and includes at least one second active device. Hence, a relatively thin insulating layer can be disposed between the capacitor electrode and the drain to reduce the area of the capacitor region and to achieve a desired aperture ratio.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: July 22, 2014
    Assignee: Au Optronics Corporation
    Inventors: Chih-Hung Lin, Wu-Liu Tsai, Chuan-Sheng Wei, Che-Chia Chang, Sheng-Chao Liu, Yu-Cheng Chen, Yi-Hui Li, Maw-Song Chen
  • Patent number: 8704966
    Abstract: A pixel array including a pixel electrode and an active device is provided. The active device includes a gate, a channel layer, a source, a drain, a connection electrode, a first branch portion and a second branch portion. The gate is electrically connected with a scan line. The channel layer located at a side of the gate is electrically isolated from the gate. The source, the drain and the connection electrode are disposed on a part region of the channel layer. The first branch portion disposed on a part region of the channel layer is connected with an end of the connection electrode. The first branch portion surrounds the source located on the channel layer. The second branch portion disposed on a part region of the channel layer is connected with the other end of the connection electrode. The second branch portion surrounds the drain located on the channel layer.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: April 22, 2014
    Assignee: Au Optronics Corporation
    Inventors: Chuan-Sheng Wei, Ming-Tao Chiang, Yu-Ting Lin, Maw-Song Chen, Wei-Ming Huang
  • Publication number: 20140042444
    Abstract: A pixel structure and a fabricating method thereof are provided. An insulating layer and a planar layer are formed on an electrode. The planar layer has a first opening. A conductive layer is formed on the planar layer and filled into the first opening. A patterned photoresist layer having an etching opening is formed. A wet etching process employing the patterned photoresist layer as a mask is performed on the conductive layer to remove the conductive layer disposed above the electrode via the etching opening and etch laterally the conductive layer below the patterned photoresist layer, to form a patterned conductive layer having a second opening. A dry etching process employing the patterned photoresist layer as a mask is performed on the insulating layer to remove the insulating layer disposed above the electrode via the etching opening, to form a patterned insulating layer having a third opening.
    Type: Application
    Filed: November 30, 2012
    Publication date: February 13, 2014
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Kuo-Yu Huang, Wei-Lun Chang, Maw-Song Chen
  • Publication number: 20140030831
    Abstract: A manufacturing method of pixel structure includes forming a first conductive layer on a substrate and forming a first insulation layer thereon; forming a second conductive layer on the first insulation layer; forming a second insulation layer on the second conductive layer; forming a semiconductor layer on the second insulation layer above the gate; forming a third conductive layer on the second insulation layer, wherein the gate, the semiconductor layer, the source, and the drain together constitute a thin film transistor, and the first electrode, the second electrode, and the third electrode together constitute a capacitor; forming a third insulation layer on the third conductive layer; and forming a pixel electrode on the third insulation layer, the pixel electrode being electrically connected to the drain.
    Type: Application
    Filed: September 27, 2013
    Publication date: January 30, 2014
    Applicant: Au Optronics Corporation
    Inventors: Chuan-Sheng Wei, Chau-Shiang Huang, Wu-Liu Tsai, Chih-Hung Lin, Maw-Song Chen
  • Patent number: 8581255
    Abstract: A pixel structure includes a first electrode on a substrate, a first insulation layer covering the first electrode, a gate located on the first insulation layer, a second electrode located on the first insulation layer above the first electrode, a second insulation layer covering the gate and the second electrode, a semiconductor layer located on the second insulation layer above the gate, a source and a drain that are located on the semiconductor layer, a third electrode, a third insulation layer, and a pixel electrode. The third electrode is located on the second insulation layer above the second electrode and electrically connected to the first electrode. The third insulation layer covers the source, the drain, and the third electrode. The pixel electrode is located on the third insulation layer and electrically connected to the drain.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: November 12, 2013
    Assignee: Au Optronics Corporation
    Inventors: Chuan-Sheng Wei, Chau-Shiang Huang, Wu-Liu Tsai, Chih-Hung Lin, Maw-Song Chen
  • Patent number: 8570480
    Abstract: A display device having slim border-area architecture is disclosed. The display device includes a substrate, a plurality of data lines, a plurality of gate lines, a plurality of auxiliary gate lines and a driving module. The substrate includes a display area and a border area. The data lines, the gate lines and the auxiliary gate lines are disposed in the display area. The driving module is disposed in the border area. The gate lines are crossed with the data lines perpendicularly. The auxiliary gate lines are parallel with the data lines. Each auxiliary gate line is electrically connected to one corresponding gate line. The data and auxiliary gate lines are electrically connected to the driving module based on an interlace arrangement. Further disclosed is a driving method for delivering gate signals provided by the driving module to the gate lines via the auxiliary gate lines.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: October 29, 2013
    Assignee: AU Optronics Corp.
    Inventors: Yi-Chen Chiang, Chih-Hung Shih, Maw-Song Chen, Tzu-Wei Ho, Ching-Huan Lin, Yu-Hsuan Li, Yao-Jen Hsieh, Ya-Ting Hsu, Chi-Mao Hung, Ken-Ming Chen, Yu-Cheng Chen
  • Patent number: 8456582
    Abstract: An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a gate insulating layer, a pixel electrode, a capacitor electrode, and a capacitor dielectric layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The gate insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the gate insulating layer. The capacitor dielectric layer is located between the capacitor electrode and the drain.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: June 4, 2013
    Assignee: Au Optronics Corporation
    Inventors: Yu-Cheng Chen, Yi-Hui Li, Chih-Hung Lin, Maw-Song Chen
  • Publication number: 20130126871
    Abstract: A pixel structure includes a first electrode on a substrate, a first insulation layer covering the first electrode, a gate located on the first insulation layer, a second electrode located on the first insulation layer above the first electrode, a second insulation layer covering the gate and the second electrode, a semiconductor layer located on the second insulation layer above the gate, a source and a drain that are located on the semiconductor layer, a third electrode, a third insulation layer, and a pixel electrode. The third electrode is located on the second insulation layer above the second electrode and electrically connected to the first electrode. The third insulation layer covers the source, the drain, and the third electrode. The pixel electrode is located on the third insulation layer and electrically connected to the drain.
    Type: Application
    Filed: February 23, 2012
    Publication date: May 23, 2013
    Applicant: Au Optronics Corporation
    Inventors: Chuan-Sheng Wei, Chau-Shiang Huang, Wu-Liu Tsai, Chih-Hung Lin, Maw-Song Chen