Abstract: A pixel structure includes a first electrode on a substrate, a first insulation layer covering the first electrode, a gate located on the first insulation layer, a second electrode located on the first insulation layer above the first electrode, a second insulation layer covering the gate and the second electrode, a semiconductor layer located on the second insulation layer above the gate, a source and a drain that are located on the semiconductor layer, a third electrode, a third insulation layer, and a pixel electrode. The third electrode is located on the second insulation layer above the second electrode and electrically connected to the first electrode. The third insulation layer covers the source, the drain, and the third electrode. The pixel electrode is located on the third insulation layer and electrically connected to the drain.

Abstract: A display panel including an active device array substrate, an opposite substrate and a display medium is provided. The active device array substrate includes a substrate, scan lines, data lines, pixel units, and data signal transmission lines. The scan lines and data lines define a plurality of pixel regions on the substrate. Each pixel unit is disposed within one of the pixel regions respectively, and each pixel unit includes a plurality of sub-pixel units. The sub-pixel units within the same pixel unit are electrically connected with the same data line, and each sub-pixel unit within the same pixel unit is electrically connected with one of the scan lines respectively. Each data signal transmission line is electrically connected with one of the data lines, and an extending direction of the data signal transmission line is substantially parallel with an extending direction of the scan lines.

Abstract: A pixel array including a pixel electrode and an active device is provided. The active device includes a gate, a channel layer, a source, a drain, a connection electrode, a first branch portion and a second branch portion. The gate is electrically connected with a scan line. The channel layer located at a side of the gate is electrically isolated from the gate. The source, the drain and the connection electrode are disposed on a part region of the channel layer. The first branch portion disposed on a part region of the channel layer is connected with an end of the connection electrode. The first branch portion surrounds the source located on the channel layer. The second branch portion disposed on a part region of the channel layer is connected with the other end of the connection electrode. The second branch portion surrounds the drain located on the channel layer.

Abstract: A driving circuit and a common electrode are located within a sealant region of the first substrate, wherein the driving circuit includes switch devices and turn-line structures. The common electrode is located within the sealant region of the first substrate. The planar layer is located on the first substrate, wherein the thickness of the planar layer at the turn-line structure of the driving circuit is less than the thicknesses of other portions. The conductive layer is located on the planar layer. A second substrate having an electrode thereon is disposed opposite to the first substrate. A liquid crystal layer is located within the display region between the first substrate and the second substrate. A sealant is located within the sealant region between the first substrate and the second substrate, and conductive balls are distributed in the sealant.

Abstract: A display panel has a display region and a peripheral region that surrounds the display region. The display panel includes a first substrate, a second substrate, a display medium, and a sealant. The first substrate has a first trench in the peripheral region, and the first trench has at least one sidewall. The second substrate is located opposite to the first substrate. The display medium is located between the first substrate and the second substrate. The sealant is located in the peripheral region between the first substrate and the second substrate. Specifically, the sealant is located in the first trench, and a distance between a sidewall of the sealant and the sidewall of the first trench ranges from about 0 um to about 700 um.

Abstract: An active array substrate, a liquid crystal display panel and a method for manufacturing the active array substrate are provided. The active array substrate includes a base, scan lines, data lines and gate tracking lines disposed on the base. Each of the gate tracking lines has first portions, auxiliary portions and junction portions, wherein the junction portion and the first portion are formed in different layers. One of the junction portions is electrically connected with corresponding one of the first portions.

Abstract: An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a first insulating layer, a pixel electrode, a capacitor electrode, and a second insulating layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The first insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the first insulating layer. The second insulating layer is located between the capacitor electrode and the drain.

Abstract: A driving circuit and a common electrode are located within a sealant region of the first substrate, wherein the driving circuit includes switch devices and turn-line structures. The common electrode is located within the sealant region of the first substrate. The planar layer is located on the first substrate, wherein the thickness of the planar layer at the turn-line structure of the driving circuit is less than the thicknesses of other portions. The conductive layer is located on the planar layer. A second substrate having an electrode thereon is disposed opposite to the first substrate. A liquid crystal layer is located within the display region between the first substrate and the second substrate. A sealant is located within the sealant region between the first substrate and the second substrate, and conductive balls are distributed in the sealant.

Abstract: An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a gate insulating layer, a pixel electrode, a capacitor electrode, and a capacitor dielectric layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The gate insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the gate insulating layer. The capacitor dielectric layer is located between the capacitor electrode and the drain.

Abstract: A driving circuit and a common electrode are located within a sealant region of the first substrate, wherein the driving circuit includes switch devices and turn-line structures. The common electrode is located within the sealant region of the first substrate. The planar layer is located on the first substrate, wherein the thickness of the planar layer at the turn-line structure of the driving circuit is less than the thicknesses of other portions. The conductive layer is located on the planar layer. A second substrate having an electrode thereon is disposed opposite to the first substrate. A liquid crystal layer is located within the display region between the first substrate and the second substrate. A sealant is located within the sealant region between the first substrate and the second substrate, and conductive balls are distributed in the sealant.

Abstract: A curved display panel includes a first substrate, a second substrate, a display medium, spacers, and padding-islands. The second substrate has a first surface and a second surface opposite to the first surface. The first surface faces toward the first substrate, and the second surface faces against the first substrate. The display medium and the spacers are disposed between the first and the second substrates. The padding-islands are disposed on a plurality of regions of the first surface of the second substrate. The padding-islands on the different regions have different thicknesses. Another curved display panel includes two substrates, a display medium, and spacing pillars. The display medium and the spacing pillars are disposed between the substrates. Bottom areas of the spacing pillars decrease from the center to the outside of the substrates along at least one first direction. Cross-sections of the substrates along the first direction are curved.

Abstract: A display panel including an active device array substrate, an opposite substrate and a display medium is provided. The active device array substrate includes a substrate, scan lines, data lines, pixel units, and data signal transmission lines. The scan lines and data lines define a plurality of pixel regions on the substrate. Each pixel unit is disposed within one of the pixel regions respectively, and each pixel unit includes a plurality of sub-pixel units. The sub-pixel units within the same pixel unit are electrically connected with the same data line, and each sub-pixel unit within the same pixel unit is electrically connected with one of the scan lines respectively. Each data signal transmission line is electrically connected with one of the data lines, and an extending direction of the data signal transmission line is substantially parallel with an extending direction of the scan lines.

Abstract: An active array substrate, a liquid crystal display panel and a method for manufacturing the active array substrate are provided. The active array substrate includes a base, scan lines, data lines and gate tracking lines disposed on the base. Each of the gate tracking lines has first portions, auxiliary portions and junction portions, wherein the junction portion and the first portion are formed in different layers. One of the junction portions is electrically connected with corresponding one of the first portions.

Abstract: A display device having slim border-area architecture is disclosed. The display device includes a substrate, a plurality of data lines, a plurality of gate lines, a plurality of auxiliary gate lines and a driving module. The substrate includes a display area and a border area. The data lines, the gate lines and the auxiliary gate lines are disposed in the display area. The driving module is disposed in the border area. The gate lines are crossed with the data lines perpendicularly. The auxiliary gate lines are parallel with the data lines. Each auxiliary gate line is electrically connected to one corresponding gate line. The data and auxiliary gate lines are electrically connected to the driving module based on an interlace arrangement. Further disclosed is a driving method for delivering gate signals provided by the driving module to the gate lines via the auxiliary gate lines.

Abstract: A pixel array includes a substrate, scan lines, data lines, active devices, first pads, second pads, first wires, second wires, an insulating layer, an organic planarization layer, first pad electrodes, second pad electrodes and pixel electrodes. The substrate has a display area and a non-display area. The scan lines and the data lines are disposed in the display area. The active devices are disposed in the display area and electrically connected to the scan lines and the data lines. The first and second pads are disposed in the non-display area. The first and second wires are disposed in the non-display area and respectively connected to the first and second pads. The organic planarization layer covers the insulating layer. The first and second pad electrodes are disposed on the organic planarization layer in the non-display area. The pixel electrodes are disposed on the organic planarization layer in the display area.

Abstract: A driving circuit and a common electrode are located within a sealant region of the first substrate, wherein the driving circuit includes switch devices and turn-line structures. The common electrode is located within the sealant region of the first substrate. The planar layer is located on the first substrate, wherein the thickness of the planar layer at the turn-line structure of the driving circuit is less than the thicknesses of other portions. The conductive layer is located on the planar layer. A second substrate having an electrode thereon is disposed opposite to the first substrate. A liquid crystal layer is located within the display region between the first substrate and the second substrate. A sealant is located within the sealant region between the first substrate and the second substrate, and conductive balls are distributed in the sealant.

Abstract: A pixel structure includes a substrate, a floating light-shielding pattern disposed on the substrate, an insulating layer disposed on the substrate and the light-shielding pattern, a data line disposed over and corresponding to the light-shielding pattern, a dielectric layer disposed on the data line and the insulating layer, and a third layer conductive pattern disposed on the dielectric layer. The third layer conductive pattern includes a common line and a common pattern. The common pattern includes two common branches arranged in parallel, and there is a space between the two common branches and over the data line.

Abstract: A pixel structure includes a substrate, a floating light-shielding pattern disposed on the substrate, an insulating layer disposed on the substrate and the light-shielding pattern, a data line disposed over and corresponding to the light-shielding pattern, a dielectric layer disposed on the data line and the insulating layer, and a third layer conductive pattern disposed on the dielectric layer. The third layer conductive pattern includes a common line and a common pattern. The common pattern includes two common branches arranged in parallel, and there is a space between the two common branches and over the data line.

Abstract: A thin film transistor liquid crystal display (TFT-LCD) and fabrication method thereof. The fabrication method includes depositing a first metal layer on a transparent substrate, patterning the first metal layer to form at least two adjacent gate electrodes, forming a gate insulating layer on the gate electrodes, forming a semiconductor layer on the insulating layer, patterning the semiconductor layer into a predetermined shape, depositing a second metal layer on the transparent substrate, patterning the second metal layer to form a source/drain electrode layer, and depositing an insulating layer on the transparent substrate. A contact hole is defined via the insulating layer, source/drain electrode layer, and gate insulating layer, exposing a part of the surface of transparent substrate between the adjacent gate electrodes. A transparent conductive layer is deposited on the transparent substrate, and a light-shielding matrix is formed directly above the contact hole.

Abstract: A thin film transistor liquid crystal display (TFT-LCD) and fabrication method thereof. The fabrication method includes depositing a first metal layer on a transparent substrate, patterning the first metal layer to form at least two adjacent gate electrodes, forming a gate insulating layer on the gate electrodes, forming a semiconductor layer on the insulating layer, patterning the semiconductor layer into a predetermined shape, depositing a second metal layer on the transparent substrate, patterning the second metal layer to form a source/drain electrode layer, and depositing an insulating layer on the transparent substrate. A contact hole is defined via the insulating layer, source/drain electrode layer, and gate insulating layer, exposing a part of the surface of transparent substrate between the adjacent gate electrodes. A transparent conductive layer is deposited on the transparent substrate, and a light-shielding matrix is formed directly above the contact hole.