Patents by Inventor Maxim S. Shatalov

Maxim S. Shatalov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160049551
    Abstract: An interface including roughness components for improving the propagation of radiation through the interface is provided. The interface includes a first profiled surface of a first layer comprising a set of large roughness components providing a first variation of the first profiled surface having a first characteristic scale and a second profiled surface of a second layer comprising a set of small roughness components providing a second variation of the second profiled surface having a second characteristic scale. The first characteristic scale is approximately an order of magnitude larger than the second characteristic scale. The surfaces can be bonded together using a bonding material, and a filler material also can be present in the interface.
    Type: Application
    Filed: June 2, 2015
    Publication date: February 18, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Publication number: 20160035936
    Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.
    Type: Application
    Filed: August 10, 2015
    Publication date: February 4, 2016
    Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Publication number: 20160027970
    Abstract: A solution for packaging an optoelectronic device using an ultraviolet transparent polymer is provided. The ultraviolet transparent polymer material can be placed adjacent to the optoelectronic device and/or a device package on which the optoelectronic device is mounted. Subsequently, the ultraviolet transparent polymer material can be processed to cause the ultraviolet transparent polymer material to adhere to the optoelectronic device and/or the device package. The ultraviolet transparent polymer can be adhered in a manner that protects the optoelectronic device from the ambient environment.
    Type: Application
    Filed: May 11, 2015
    Publication date: January 28, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Saulius Smetona, Alexander Dobrinsky, Michael Shur
  • Patent number: 9184346
    Abstract: A contact including an ohmic layer and a reflective layer located on the ohmic layer is provided. The ohmic layer is transparent to radiation having a target wavelength, while the reflective layer is at least approximately eighty percent reflective of radiation having the target wavelength. The target wavelength can be ultraviolet light, e.g., having a wavelength within a range of wavelengths between approximately 260 and approximately 360 nanometers.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: November 10, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexander Lunev, Alexander Dobrinsky, Maxim S. Shatalov, Remigijus Gaska, Michael Shur
  • Patent number: 9184339
    Abstract: A method of fabricating a light emitting diode, which includes an n-type contact layer and a light generating structure adjacent to the n-type contact layer, is provided. The light generating structure includes a set of quantum wells. The contact layer and light generating structure can be configured so that a difference between an energy of the n-type contact layer and an electron ground state energy of a quantum well is greater than an energy of a polar optical phonon in a material of the light generating structure. Additionally, the light generating structure can be configured so that its width is comparable to a mean free path for emission of a polar optical phonon by an electron injected into the light generating structure.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: November 10, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Maxim S Shatalov, Michael Shur, Alexander Dobrinsky
  • Publication number: 20150297767
    Abstract: A system for sterilizing at least one surface of an object is provided. The system includes a set of ultraviolet radiation sources and a set of wave guiding structures configured to direct ultraviolet radiation having a set of target attributes to a desired location on at least one surface of the object. The set of wave guiding structures can include at least one ultraviolet reflective surface having an ultraviolet reflection coefficient of at least thirty percent. Furthermore, the system can include a computer system for operating the ultraviolet radiation sources to deliver a target dose of ultraviolet radiation to the at least one target surface of the object.
    Type: Application
    Filed: June 23, 2015
    Publication date: October 22, 2015
    Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Remigijus Gaska, Michael Shur, Alexander Dobrinsky, Timothy James Bettles, Maxim S. Shatalov
  • Publication number: 20150295133
    Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
    Type: Application
    Filed: April 15, 2015
    Publication date: October 15, 2015
    Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Daniel D. Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Publication number: 20150295155
    Abstract: A structured substrate configured for epitaxial growth of a semiconductor layer thereon is provided. Structures can be formed on a side of the structured substrate opposite that of the growth surface for the semiconductor layer. The structures can include cavities and/or pillars, which can be patterned, randomly distributed, and/or the like. The structures can be configured to modify one or more properties of the substrate material such that growth of a higher quality semiconductor layer can be obtained.
    Type: Application
    Filed: April 10, 2015
    Publication date: October 15, 2015
    Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Michael Shur, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska
  • Publication number: 20150295127
    Abstract: A composite substrate configured for epitaxial growth of a semiconductor layer thereon is provided. The composite substrate includes multiple substrate layers formed of different materials having different thermal expansion coefficients. The thermal expansion coefficient of the material of the semiconductor layer can be between the thermal coefficients of the substrate layer materials. The composite substrate can have a composite thermal expansion coefficient configured to reduce an amount of tensile stress within the semiconductor layer at room temperature and/or an operating temperature for a device fabricated using the heterostructure.
    Type: Application
    Filed: April 10, 2015
    Publication date: October 15, 2015
    Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Michael Shur, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska
  • Patent number: 9142741
    Abstract: A profiled surface for improving the propagation of radiation through an interface is provided. The profiled surface includes a set of large roughness components providing a first variation of the profiled surface having a characteristic scale approximately an order of magnitude larger than a target wavelength of the radiation. The profiled surface also includes a set of small roughness components superimposed on the set of large roughness components and providing a second variation of the profiled surface having a characteristic scale on the order of the target wavelength of the radiation.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: September 22, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Publication number: 20150255672
    Abstract: A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.
    Type: Application
    Filed: May 26, 2015
    Publication date: September 10, 2015
    Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Michael Shur, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Jinwei Yang
  • Publication number: 20150243841
    Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
    Type: Application
    Filed: February 22, 2015
    Publication date: August 27, 2015
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Publication number: 20150228855
    Abstract: A profiled surface for improving the propagation of radiation through an interface is provided. The profiled surface includes a set of large roughness components providing a first variation of the profiled surface having a characteristic scale approximately an order of magnitude larger than a target wavelength of the radiation. The set of large roughness components can include a series of truncated shapes. The profiled surface also includes a set of small roughness components superimposed on the set of large roughness components and providing a second variation of the profiled surface having a characteristic scale on the order of the target wavelength of the radiation.
    Type: Application
    Filed: June 6, 2014
    Publication date: August 13, 2015
    Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9105792
    Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: August 11, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Publication number: 20150179751
    Abstract: A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.
    Type: Application
    Filed: March 3, 2015
    Publication date: June 25, 2015
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Mikhail Gaevski, Grigory Simin, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9061082
    Abstract: A system for sterilizing at least one surface of an object is provided. The system includes a set of ultraviolet radiation sources and a set of wave guiding structures configured to direct ultraviolet radiation having a set of target attributes to a desired location on at least one surface of the object. The set of wave guiding structures can include at least one ultraviolet reflective surface having an ultraviolet reflection coefficient of at least thirty percent. Furthermore, the system can include a computer system for operating the ultraviolet radiation sources to deliver a target dose of ultraviolet radiation to the at least one target surface of the object.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: June 23, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Michael Shur, Alexander Dobrinsky, Timothy James Bettles, Maxim S Shatalov
  • Publication number: 20150165079
    Abstract: Ultraviolet radiation is directed within an area. Items located within the area and/or one or more conditions of the area are monitored over a period of time. Based on the monitoring, ultraviolet radiation sources are controlled by adjusting a direction, an intensity, a pattern, and/or a spectral power of the ultraviolet radiation generated by the ultraviolet radiation source. Adjustments to the ultraviolet radiation source(s) can correspond to one of a plurality of selectable operating configurations including a storage life preservation operating configuration, a disinfection operating configuration, and an ethylene decomposition operating configuration.
    Type: Application
    Filed: February 24, 2015
    Publication date: June 18, 2015
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Maxim S. Shatalov, Timothy James Bettles, Yuri Bilenko, Saulius Smetona, Alexander Dobrinsky, Remigijus Gaska, Igor Agafonov
  • Patent number: 9048378
    Abstract: An interface including roughness components for improving the propagation of radiation through the interface is provided. The interface includes a first profiled surface of a first layer comprising a set of large roughness components providing a first variation of the first profiled surface having a first characteristic scale and a second profiled surface of a second layer comprising a set of small roughness components providing a second variation of the second profiled surface having a second characteristic scale. The first characteristic scale is approximately an order of magnitude larger than the second characteristic scale. The surfaces can be bonded together using a bonding material, and a filler material also can be present in the interface.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: June 2, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9042420
    Abstract: A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: May 26, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Jinwei Yang
  • Publication number: 20150108428
    Abstract: A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more composite semiconductor layers. The composite semiconductor layer can include sub-layers of varying morphology, at least one of which can be formed by a group of columnar structures (e.g., nanowires). Another sub-layer in the composite semiconductor layer can be porous, continuous, or partially continuous.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 23, 2015
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska