Patents by Inventor Maxim S. Shatalov

Maxim S. Shatalov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device with Transparent and Higher Conductive Regions in Lateral Cross Section of Semiconductor Layer
    Publication number: 20170186910
    Abstract: A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.
    Type: Application
    Filed: March 13, 2017
    Publication date: June 29, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Jinwei Yang
  • Patterned layer design for group III nitride layer growth
    Patent number: 9691939
    Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: June 27, 2017
    Assignee: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Structured substrate
    Patent number: 9691680
    Abstract: A structured substrate configured for epitaxial growth of a semiconductor layer thereon is provided. Structures can be formed on a side of the structured substrate opposite that of the growth surface for the semiconductor layer. The structures can include cavities and/or pillars, which can be patterned, randomly distributed, and/or the like. The structures can be configured to modify one or more properties of the substrate material such that growth of a higher quality semiconductor layer can be obtained.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: June 27, 2017
    Assignee: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Michael Shur, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska
  • Semiconductor Heterostructure with Stress Management
    Publication number: 20170179335
    Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 22, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Daniel Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patterned layer design for group III nitride layer growth
    Patent number: 9680061
    Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: June 13, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur
  • Ohmic contact to semiconductor layer
    Patent number: 9660043
    Abstract: A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: May 23, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Mikhail Gaevski, Grigory Simin, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Group III nitride heterostructure for optoelectronic device
    Patent number: 9660133
    Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: May 23, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Optoelectronic device with modulation doping
    Patent number: 9653631
    Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: May 16, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Stress relieving semiconductor layer
    Patent number: 9653313
    Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: May 16, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Wenhong Sun, Rakesh Jain, Michael Shur, Remigijus Gaska
  • Optoelectronic device with modulation doping
    Patent number: 9647168
    Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: May 9, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Composite substrate
    Patent number: 9646911
    Abstract: A composite substrate configured for epitaxial growth of a semiconductor layer thereon is provided. The composite substrate includes multiple substrate layers formed of different materials having different thermal expansion coefficients. The thermal expansion coefficient of the material of the semiconductor layer can be between the thermal coefficients of the substrate layer materials. The composite substrate can have a composite thermal expansion coefficient configured to reduce an amount of tensile stress within the semiconductor layer at room temperature and/or an operating temperature for a device fabricated using the heterostructure.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: May 9, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska
  • Patterned substrate design for layer growth
    Patent number: 9634189
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 25, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Semiconductor material doping
    Patent number: 9634183
    Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: April 25, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Remigijus Gaska, Jinwei Yang, Michael Shur, Alexander Dobrinsky
  • Semiconductor Structure with Stress-Reducing Buffer Structure
    Publication number: 20170110628
    Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Storage Device Including Ultraviolet Illumination
    Publication number: 20170100495
    Abstract: Ultraviolet radiation is directed within an area. Items located within the area and/or one or more conditions of the area are monitored over a period of time. Based on the monitoring, ultraviolet radiation sources are controlled by adjusting a direction, an intensity, a pattern, and/or a spectral power of the ultraviolet radiation generated by the ultraviolet radiation source. Adjustments to the ultraviolet radiation source(s) can correspond to one of a plurality of selectable operating configurations including a storage life preservation operating configuration, a disinfection operating configuration, and an ethylene decomposition operating configuration.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 13, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Maxim S. Shatalov, Timothy James Bettles, Yuri Bilenko, Saulius Smetona, Alexander Dobrinsky, Remigijus Gaska, Igor Agafonov
  • Device Including Transparent Layer with Profiled Surface for Improved Extraction
    Publication number: 20170104131
    Abstract: A profiled surface for improving the propagation of radiation through an interface is provided. The profiled surface includes a set of large roughness components providing a first variation of the profiled surface having a characteristic scale approximately an order of magnitude larger than a target wavelength of the radiation. The set of large roughness components can include a series of truncated shapes. The profiled surface also includes a set of small roughness components superimposed on the set of large roughness components and providing a second variation of the profiled surface having a characteristic scale on the order of the target wavelength of the radiation.
    Type: Application
    Filed: December 26, 2016
    Publication date: April 13, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patterned Layer Design for Group III Nitride Layer Growth
    Publication number: 20170104129
    Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Application
    Filed: December 23, 2016
    Publication date: April 13, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Ultraviolet System for Disinfection
    Publication number: 20170100496
    Abstract: Ultraviolet radiation is directed within an area. The target wavelength ranges and/or target intensity ranges of the ultraviolet radiation sources can correspond to at least one of a plurality of selectable operating configurations including a sterilization operating configuration and a preservation operating configuration.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 13, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Maxim S. Shatalov, Timothy James Bettles, Yuri Bilenko, Alexander Dobrinsky, Remigijus Gaska
  • Ultraviolet Device Encapsulant
    Publication number: 20170104140
    Abstract: A composite material, which can be used as an encapsulant for an ultraviolet device, is provided. The composite material includes a matrix material and at least one filler material incorporated in the matrix material that are both at least partially transparent to ultraviolet radiation of a target wavelength. The filler material includes microparticles and/or nanoparticles and can have a thermal coefficient of expansion significantly smaller than a thermal coefficient of expansion of the matrix material for relevant atmospheric conditions. The relevant atmospheric conditions can include a temperature and a pressure present during each of: a curing and a cool down process for fabrication of a device package including the composite material and normal operation of the ultraviolet device within the device package.
    Type: Application
    Filed: December 23, 2016
    Publication date: April 13, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Maxim S. Shatalov, Alexander Dobrinsky, Jinwei Yang, Michael Shur
  • Epitaxy Technique for Growing Semiconductor Compounds
    Publication number: 20170104132
    Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 13, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur