Patents by Inventor Maxim S. Shatalov

Maxim S. Shatalov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9337387
    Abstract: A profiled surface for improving the propagation of radiation through an interface is provided. The profiled surface includes a set of large roughness components providing a first variation of the profiled surface having a characteristic scale approximately an order of magnitude larger than a target wavelength of the radiation. The set of large roughness components can include a series of truncated shapes. The profiled surface also includes a set of small roughness components superimposed on the set of large roughness components and providing a second variation of the profiled surface having a characteristic scale on the order of the target wavelength of the radiation.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: May 10, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9331244
    Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 3, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S Shatalov, Alexander Dobrinsky, Alexander Lunev, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Patent number: 9330906
    Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 3, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Wenhong Sun, Rakesh Jain, Michael Shur, Remigijus Gaska
  • Publication number: 20160118531
    Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.
    Type: Application
    Filed: November 18, 2015
    Publication date: April 28, 2016
    Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Publication number: 20160118534
    Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Jinwei Yang, Remigijus Gaska, Mikhail Gaevski
  • Publication number: 20160118536
    Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher. In one embodiment, the semiconductor layer is used to form an optoelectronic device.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Alexander Lunev, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Publication number: 20160118535
    Abstract: A contact to a semiconductor layer in a light emitting structure is provided. The contact can include a plurality of contact areas formed of a metal and separated by a set of voids. The contact areas can be separated from one another by a characteristic distance selected based on a set of attributes of a semiconductor contact structure of the contact and a characteristic contact length scale of the contact. The voids can be configured to increase an overall reflectivity or transparency of the contact.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Alexander Lunev, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9324560
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: April 26, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Publication number: 20160111618
    Abstract: A heterostructure for use in fabricating an optoelectronic device with improved thermal management is provided. The heterostructure can include a plurality of epitaxially grown layers including an n-type contact layer, an active layer, and a p-type contact layer. N-type and p-type electrodes for the n-type contact layer and p-type contact layer, respectively, can be embedded within an electrically insulating, thermally conductive semiconductor layer that is adjacent to the epitaxially grown layers. The electrically insulating, thermally conductive semiconductor layer can provide a larger lateral area for extracting heat generated by the active layer, so that there is improved thermal management within the device.
    Type: Application
    Filed: May 7, 2015
    Publication date: April 21, 2016
    Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Michael Shur, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska
  • Publication number: 20160104784
    Abstract: A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged.
    Type: Application
    Filed: December 17, 2015
    Publication date: April 14, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Michael Shur, Jinwei Yang, Alexander Dobrinsky, Maxim S. Shatalov
  • Patent number: 9312428
    Abstract: A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: April 12, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9312448
    Abstract: A contact to a semiconductor layer in a light emitting structure is provided. The contact can include a plurality of contact areas formed of a metal and separated by a set of voids. The contact areas can be separated from one another by a characteristic distance selected based on a set of attributes of a semiconductor contact structure of the contact and a characteristic contact length scale of the contact. The voids can be configured to increase an overall reflectivity or transparency of the contact.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: April 12, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexander Lunev, Maxim S Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Publication number: 20160093771
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.
    Type: Application
    Filed: March 17, 2015
    Publication date: March 31, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Patent number: 9287442
    Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 15, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S Shatalov, Remigijus Gaska, Jinwei Yang, Michael Shur, Alexander Dobrinsky
  • Patent number: 9287449
    Abstract: A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: March 15, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Maxim S. Shatalov, Alexander Lunev, Alexander Dobrinsky, Jinwei Yang, Michael Shur
  • Patent number: 9281441
    Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 8, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Jinwei Yang, Remigijus Gaska
  • Publication number: 20160064631
    Abstract: A solution for packaging an optoelectronic device using an ultraviolet transparent polymer is provided. The ultraviolet transparent polymer material can be placed adjacent to the optoelectronic device and/or a device package on which the optoelectronic device is mounted. Subsequently, the ultraviolet transparent polymer material can be processed to cause the ultraviolet transparent polymer material to adhere to the optoelectronic device and/or the device package. The ultraviolet transparent polymer can be adhered in a manner that protects the optoelectronic device from the ambient environment.
    Type: Application
    Filed: November 11, 2015
    Publication date: March 3, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Saulius Smetona, Alexander Dobrinsky, Michael Shur, Mikhail Gaevski
  • Publication number: 20160064601
    Abstract: A method of fabricating a light emitting diode, which includes an n-type contact layer and a light generating structure adjacent to the n-type contact layer, is provided. The light generating structure includes a set of quantum wells. The contact layer and light generating structure can be configured so that a difference between an energy of the n-type contact layer and an electron ground state energy of a quantum well is greater than an energy of a polar optical phonon in a material of the light generating structure. Additionally, the light generating structure can be configured so that its width is comparable to a mean free path for emission of a polar optical phonon by an electron injected into the light generating structure.
    Type: Application
    Filed: November 9, 2015
    Publication date: March 3, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Maxim S. Shatalov, Michael Shur, Alexander Dobrinsky
  • Publication number: 20160058020
    Abstract: Ultraviolet radiation is directed within an area. The target wavelength ranges and/or target intensity ranges of the ultraviolet radiation sources can correspond to at least one of a plurality of selectable operating configurations including a sterilization operating configuration and a preservation operating configuration.
    Type: Application
    Filed: November 10, 2015
    Publication date: March 3, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Maxim S. Shatalov, Timothy James Bettles, Yuri Bilenko, Alexander Dobrinsky, Remigijus Gaska
  • Patent number: 9269788
    Abstract: A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 23, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Michael Shur, Jinwei Yang, Alexander Dobrinsky, Maxim S Shatalov