Patents by Inventor Maxim S. Shatalov

Maxim S. Shatalov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patterned layer design for group III nitride layer growth
    Patent number: 9806228
    Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: October 31, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Semiconductor heterostructure with stress management
    Patent number: 9799793
    Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 24, 2017
    Assignee: Sensor Electronics Technology, Inc.
    Inventors: Daniel Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Metallic contact for optoelectronic semiconductor device
    Patent number: 9793439
    Abstract: A contact to a semiconductor layer in a light emitting structure is provided. The contact can include a plurality of contact areas formed of a metal and separated by a set of voids. The contact areas can be separated from one another by a characteristic distance selected based on a set of attributes of a semiconductor contact structure of the contact and a characteristic contact length scale of the contact. The voids can be configured to increase an overall reflectivity or transparency of the contact.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: October 17, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexander Lunev, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patterned Layer Design for Group III Nitride Layer Growth
    Publication number: 20170287698
    Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-Ill nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 5, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Ultraviolet reflective rough adhesive contact
    Patent number: 9768357
    Abstract: A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: September 19, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Maxim S. Shatalov, Alexander Dobrinsky, Jinwei Yang, Michael Shur, Grigory Simin
  • Optoelectronic Device with Modulation Doping
    Publication number: 20170263805
    Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.
    Type: Application
    Filed: May 8, 2017
    Publication date: September 14, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Group III Nitride Heterostructure for Optoelectronic Device
    Publication number: 20170256672
    Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.
    Type: Application
    Filed: May 23, 2017
    Publication date: September 7, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Perforating Contact to Semiconductor Layer
    Publication number: 20170256623
    Abstract: A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 7, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Mikhail Gaevski, Grigory Simin, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Semiconductor layer including compositional inhomogeneities
    Patent number: 9748440
    Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: August 29, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Jinwei Yang, Remigijus Gaska, Mikhail Gaevski
  • Device with inverted large scale light extraction structures
    Patent number: 9741899
    Abstract: An interface including roughness components for improving the propagation of radiation through the interface is provided. The interface includes a first profiled surface of a first layer comprising a set of large roughness components providing a first variation of the first profiled surface having a first characteristic scale and a second profiled surface of a second layer comprising a set of small roughness components providing a second variation of the second profiled surface having a second characteristic scale. The first characteristic scale is approximately an order of magnitude larger than the second characteristic scale. The surfaces can be bonded together using a bonding material, and a filler material also can be present in the interface.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: August 22, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Semiconductor heterostructure with stress management
    Patent number: 9735315
    Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: August 15, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Daniel Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Stress Relieving Semiconductor Layer
    Publication number: 20170229611
    Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
    Type: Application
    Filed: April 25, 2017
    Publication date: August 10, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Wenhong Sun, Rakesh Jain, Michael Shur, Remigijus Gaska
  • Patterned Substrate Design for Layer Growth
    Publication number: 20170229612
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Semiconductor Material Doping
    Publication number: 20170229610
    Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Remigijus Gaska, Jinwei Yang, Michael Shur, Alexander Dobrinsky
  • Storage device including target UV illumination ranges
    Patent number: 9724441
    Abstract: Ultraviolet radiation is directed within an area at target wavelengths, target intensities, a target temporal distribution, and/or a target spatial distribution. The target attribute(s) of the ultraviolet radiation can correspond to at least one of a plurality of selectable operating configurations including a storage life preservation operating configuration, a disinfection operating configuration, an ethylene decomposition operating configuration, and/or the like.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: August 8, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Maxim S. Shatalov, Timothy James Bettles, Yuri Bilenko, Saulius Smetona, Alexander Dobrinsky, Remigijus Gaska
  • Curing Ultraviolet Sensitive Polymer Materials
    Publication number: 20170218208
    Abstract: An approach for curing ultraviolet sensitive polymer materials (e.g., polymer inks, coatings, and adhesives) using ultraviolet radiation is disclosed. The ultraviolet sensitive polymer materials curing can utilize ultraviolet light at different wavelength emissions arranged in a random, mixed or sequential arrangement. In one embodiment, an ultraviolet light C (UV-C) radiation emitter having a set of UV-C sources that emit UV-C radiation at a predetermined UV-C duration and intensity operate in conjunction with an ultraviolet light B (UV-B) radiation emitter having a set of UV-B sources configured to emit UV-B radiation at a predetermined UV-B duration and intensity and/or an ultraviolet light A (UV-A) radiation emitter having a set of UV-A sources configured to emit UV-A radiation at a predetermined UV-A duration and intensity, to cure the ultraviolet sensitive polymer materials.
    Type: Application
    Filed: February 2, 2017
    Publication date: August 3, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Timothy James Bettles, Michael Shur, Alexander Dobrinsky, Maxim S. Shatalov
  • Non-uniform multiple quantum well structure
    Patent number: 9722139
    Abstract: A light emitting heterostructure including one or more fine structure regions is provided. The light emitting heterostructure can include a plurality of barriers alternating with a plurality of quantum wells. One or more of the barriers and/or quantum wells includes a fine structure region. The fine structure region includes a plurality of subscale features arranged in at least one of: a growth or a lateral direction.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: August 1, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Wenhong Sun, Alexander Dobrinsky, Maxim S Shatalov, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Ultraviolet system for disinfection
    Patent number: 9707307
    Abstract: Ultraviolet radiation is directed within an area. The target wavelength ranges and/or target intensity ranges of the ultraviolet radiation sources can correspond to at least one of a plurality of selectable operating configurations including a sterilization operating configuration and a preservation operating configuration.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: July 18, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Maxim S. Shatalov, Timothy James Bettles, Yuri Bilenko, Alexander Dobrinsky, Remigijus Gaska
  • Solid-State Lighting Structure With Integrated Control
    Publication number: 20170196061
    Abstract: A solid-state light source (SSLS) structure with integrated control. In one embodiment, a SSLS control circuit can be integrated with a SSLS structure formed from a multiple of SSLSs. The SSLS control circuit controls the total operating current of the SSLS structure to within a predetermined total operating current limit by selectively limiting the current in individual SSLSs or in groups of SSLSs as each are turned on according to a sequential order. The SSLS control circuit limits the current in each of the individual SSLSs or groups of SSLSs as function of the saturation current of the SSLSs. In one embodiment, the individual SSLSs or groups of SSLSs has a turn on voltage corresponding to a voltage causing a preceding SSLS or group of SSLSs in the sequential order to saturate current.
    Type: Application
    Filed: December 21, 2016
    Publication date: July 6, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Alexander Dobrinsky, Maxim S. Shatalov
  • Heterostructure Including Anodic Aluminum Oxide Layer
    Publication number: 20170186905
    Abstract: A semiconductor structure including an anodic aluminum oxide layer is described. The anodic aluminum oxide layer can include a plurality of pores extending to an adjacent surface of the semiconductor structure. A filler material can penetrate at least some of the plurality of pores and directly contact the surface of the semiconductor structure. In an illustrative embodiment, multiple types of filler material at least partially fill the pores of the aluminum oxide layer.
    Type: Application
    Filed: August 19, 2016
    Publication date: June 29, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Maxim S. Shatalov, Alexander Dobrinsky