Abstract: An integrated system for sequencing a string of oligo-nucleotides is disclosed, the system includes a sequencer for sequencing a plurality of fragments of the string of oligo-nucleotides via identifying oligo-nucleotides of the fragments one by one and a processor for processing the identified oligo-nucleotides to determine the sequence of the string of oligo-nucleotides and to stop the sequencer from sequencing redundant fragments, where the sequencer and the processor operate in a cycle for each oligo-nucleotide of the fragments.

Abstract: A two-walled coupled inductor includes an outer wall and an inner wall separated by a slit. The outer wall has a first width and the inner wall has a second width The inner wall and the outer wall may be configured to be coupled to oscillator circuitry. The two-walled coupled inductor may include an electrically conductive stub coupled to the outer wall to be coupled to a power supply. A common mode current flows through the outer wall, and the stub if one is present, and a differential mode current flows through both the outer wall and the inner wall, but not the stub. The first and second widths, and dimensions of the stub, may be sized to increase an inductance of the common mode compared to an inductance of the differential mode, thereby reducing phase noise of the inductor-based resonator.

Abstract: An example method for active load modulation includes determining a modulated portion and an unmodulated portion of a bit. Further, the example method includes during the modulated portion of the bit, holding a phase of a received carrier signal. In addition, the example method includes, during the unmodulated portion of the bit, synchronizing to the received carrier signal.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for reducing flicker noise, power consumption, and/or frequency pulling in voltage-controlled oscillators (VCOs). One example VCO generally includes an active negative transconductance circuit and a resonant circuit connected between a voltage rail for the VCO and the active negative transconductance circuit, wherein the resonant circuit is configured to resonate at a frequency of an oscillating signal generated by the VCO.

Abstract: Differential crystal oscillator circuits are disclosed that may provide low-power, low phase noise operation, and prevent latching at low frequency by providing a low impedance DC path using active super diodes.

Abstract: A circuit includes: first and second output terminals; a reference resonator coupled between the first and second output terminals; a cross-coupled oscillation unit coupled to the first and second output terminals; a first MOSFET diode coupled to the cross-coupled oscillation unit, the first MOSFET diode including a first transistor, a first resistor coupled between gate and drain terminals of the first transistor, and a first capacitor; a second MOSFET diode coupled to the cross-coupled oscillation unit, the second MOSFET diode including a second transistor, a second resistor coupled between gate and drain terminals of the second transistor, and a second capacitor cross coupled between the drain terminal of the second transistor and the gate terminal of the first transistor, wherein the first capacitor is cross coupled between the drain terminal of the first transistor and the gate terminal of the second transistor.

Abstract: A circuit includes: first and second output terminals; a reference resonator coupled between the first and second output terminals; a cross-coupled oscillation unit coupled to the first and second output terminals; a first MOSFET diode coupled to the cross-coupled oscillation unit, the first MOSFET diode including a first transistor, a first resistor coupled between gate and drain terminals of the first transistor, and a first capacitor; a second MOSFET diode coupled to the cross-coupled oscillation unit, the second MOSFET diode including a second transistor, a second resistor coupled between gate and drain terminals of the second transistor, and a second capacitor cross coupled between the drain terminal of the second transistor and the gate terminal of the first transistor, wherein the first capacitor is cross coupled between the drain terminal of the first transistor and the gate terminal of the second transistor.

Abstract: Techniques for providing transformer-based CMOS oscillators capable of operation with low voltage power supplies. In an exemplary embodiment, an LC tank is provided at the drains of a transistor pair, and the inductance of the LC tank is mutually magnetically coupled to an inductance between the gates of the transistor pair. A separate complementary transistor pair is also coupled to the LC tank. A further exemplary embodiment provides an LC tank at the gates of a transistor pair, as well as for three-way coupling amongst a tank inductance, an inductance between the gates of the transistor pair, and an inductance between the gates of a complementary transistor pair.

Abstract: Systems and methods for biasing frequency oscillators to minimize phase noise are disclosed. The system may comprise a tank circuit having an inductor, at least a first coupling capacitor and a second coupling capacitor. The system may further comprise a varactor circuit electrically connected to the first coupling capacitor and the second coupling capacitor. The system may further comprise at least one first metal oxide semiconductor (MOS) device electrically connected in shunt with the tank circuit and a bias voltage. The at least one first MOS device may be electrically connected to a first gate bias voltage configured to bias the at least one first MOS device such that a first gate-to-source voltage of the at least one first MOS device remains below the first threshold voltage.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for using multiple voltage-controlled oscillators (VCOs) to increase frequency synthesizer performance, such as in stringent multiple-input, multiple-output (MIMO) modes. One example apparatus capable of generating oscillating signals generally includes a first VCO, a second VCO, and connection circuitry configured to connect the second VCO in parallel with the first VCO if a phase-locked loop (PLL) associated with the second VCO is idle.

Abstract: An example method for active load modulation includes determining a modulated portion and an unmodulated portion of a bit. Further, the example method includes during the modulated portion of the bit, holding a phase of a received carrier signal. In addition, the example method includes, during the unmodulated portion of the bit, synchronizing to the received carrier signal.

Abstract: Systems and methods for biasing frequency oscillators to minimize phase noise are disclosed. The system may comprise a tank circuit having an inductor, at least a first coupling capacitor and a second coupling capacitor. The system may further comprise a varactor circuit electrically connected to the first coupling capacitor and the second coupling capacitor. The system may further comprise at least one first metal oxide semiconductor (MOS) device electrically connected in shunt with the tank circuit and a bias voltage. The at least one first MOS device may be electrically connected to a first gate bias voltage configured to bias the at least one first MOS device such that a first gate-to-source voltage of the at least one first MOS device remains below the first threshold voltage.

Abstract: A transformer is described. The transformer includes a primary coil and a first secondary coil. A first coupling occurs between the first secondary coil and the primary coil. The transformer also includes a second secondary coil. A second coupling occurs between the second secondary coil and the primary coil. The first secondary coil is separated from the second secondary coil to prevent coupling between the first secondary coil and the second secondary coil. A first width of the first secondary coil is configured independently of a second width of the second secondary coil.

Abstract: Transceivers implemented with a combination of super-heterodyne and zero intermediate frequency (ZIF) topologies are disclosed. In an exemplary design, an apparatus includes a frequency conversion circuit and a local oscillator (LO) generator. The LO generator generates a first LO signal and a second LO signal. The frequency conversion circuit performs frequency conversion (i) between intermediate frequency (IF) and baseband, based on the first LO signal, for an IF signal and (ii) between radio frequency (RF) and baseband, based on the second LO signal, for an RF signal. The frequency conversion circuit may perform frequency downconversion (i) from IF to baseband for a super-heterodyne receiver and (ii) from RF to baseband for a ZIF receiver. Alternatively or additionally, the frequency conversion circuit may perform frequency upconversion (i) from baseband to IF for a super-heterodyne transmitter and (ii) from baseband to RF for a ZIF transmitter.

Abstract: Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor having a gate, a source connected with a first node of the circuit, and a drain connected with a second node of the circuit. The circuit may also include a voltage-limiting device connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.

Abstract: A method for inductively coupled communication is described. The method includes generating a first signal. The first signal frequency is a first integer multiple of a carrier frequency for inductively coupled communication. The method also includes selecting between a standalone mode and a coexistence mode. The method further includes dividing the first signal to obtain a second signal when in standalone mode. The second signal frequency is a second integer multiple of the carrier frequency. The method additionally includes dividing the first signal to obtain a third signal when in coexistence mode. The third signal frequency is a third integer multiple of the carrier frequency. The method also includes generating an inductively coupled communication signal using at least one of the second signal and the third signal.

Abstract: A DC offset filter for wide band beamforming receivers is disclosed. In an exemplary embodiment, an apparatus includes a first mixer configured to down-convert an RF wideband beamformed signal to generate a first baseband wideband beamformed signal, the RF wideband beamformed signal having a beam pattern selected from a plurality of beam patterns, and a notch filter configured to remove DC offset from the first baseband wideband beamformed signal independent of the beam pattern.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for using multiple voltage-controlled oscillators (VCOs) to increase frequency synthesizer performance, such as in stringent multiple-input, multiple-output (MIMO) modes. One example apparatus capable of generating oscillating signals generally includes a first VCO, a second VCO, and connection circuitry configured to connect the second VCO in parallel with the first VCO if a phase-locked loop (PLL) associated with the second VCO is idle.

Abstract: Certain aspects of the present disclosure provide circuits for generating high accuracy millimeter wave or radio frequency (RF) wideband in-phase (I) and quadrature (Q) oscillating signals having acceptable amplitude and phase mismatch over process, voltage, and temperature (PVT) variations with reduced cost, area, and power consumption. In one example apparatus, a polyphase filter having a first stage and a second stage is provided. Each stage comprises resistive elements and capacitive elements. Certain aspects of the present disclosure provide for intentional resistive and/or capacitive value mismatch between the resistive or capacitive values of one or multiple stages such that the phase mismatch between the resulting I and Q signals may be reduced without degrading the amplitude mismatch. Certain aspects of the present disclosure provide for replacing the resistive elements in at least one stage with transistors operating in the triode region, where the on-resistance is controlled by a feedback network.

Abstract: An apparatus includes a main amplifier configured to receive an input signal. The main amplifier is also configured to generate an output signal. The apparatus also includes an auxiliary path configured to phase-shift the input signal to generate a cancellation signal to reduce or cancel a blocker component of the output signal.