Patents by Inventor Md Altaf HOSSAIN

Md Altaf HOSSAIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11070209
    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Dheeraj Subbareddy, Md Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
  • Patent number: 11056452
    Abstract: An IC includes first, second, and third IOs, and a multiplexer that includes first and second inputs, and an output. The IC includes first and second transmitters respectively having an output coupled to the first IO and an output coupled to the second IO. A clock generator is coupled between the output and an input of the first transmitter and between the output and an input of the second transmitter. The first input may receive a clock signal generated by the first clock generator and the second clock input is coupled to the third IO and may receive a clock signal via the third IO element from another IC. An IC includes a programmable fabric, k*n wires coupled to and extending from the fabric, n TDMs, and n IO blocks. Each TDM includes k inputs coupled to k wires and an output coupled to one of the IO blocks.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Dheeraj Subbareddy, Ankireddy Nalamalpu, Md Altaf Hossain
  • Publication number: 20210183775
    Abstract: Disclosed embodiments include die-edge level passive devices for integrated-circuit device packages that provide a low-loss path to active and passive devices, by minimizing inductive loops.
    Type: Application
    Filed: September 17, 2020
    Publication date: June 17, 2021
    Inventors: Min Suet Lim, Eng Huat Goh, MD Altaf Hossain
  • Publication number: 20210185830
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Application
    Filed: February 26, 2021
    Publication date: June 17, 2021
    Inventors: MD Altaf HOSSAIN, Scott A. GILBERT
  • Patent number: 10980134
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Patent number: 10950537
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Scott Gilbert
  • Publication number: 20210066178
    Abstract: An integrated circuit package may include a semiconductor die on a first side of the integrated circuit package, a first ball grid array (BGA) connection on the first side of the integrated circuit package, and a second BGA connection on a second side of the integrated circuit package. The integrated circuit package may include one or more traces that route data from the first BGA connection and the second BGA connection.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Inventors: MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Dinesh Somasekhar
  • Publication number: 20200402937
    Abstract: An integrated circuit package may be formed comprising an interposer with a center die and a plurality of identical integrated circuit dice positioned around the center die and attached to the interposer, wherein the center die is the switch/router for the plurality of identical integrated circuit dice. The interposer comprises a substrate, a central pattern of bond pads formed in or on the substrate for attaching the center die, and substantially identical satellite patterns formed in or on the substrate for attaching identical integrated circuit dice. The central pattern of bond pads has repeating sets of a specific geometric pattern and wherein the identical satellite patterns of bond pads are positioned to form the same geometric pattern as the specific geometric pattern of the central pattern of bond pads. Thus, substantially identical conductive routes may be formed between the center die and each of the identical integrated circuit dice.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Applicant: Intel Corporation
    Inventors: Robert Sankman, Dheeraj Subbareddy, Md Altaf Hossain, Ankireddy Nalamalpu
  • Publication number: 20200357721
    Abstract: An integrated circuit structure that includes a first integrated circuit package and a second integrated circuit package is described. The two packages can be stacked above, for example, a printed circuit board. The top package is inverted, such that a first die of that top package is facing a second die of the bottom package. A cooling arrangement is in a gap between the first and second integrated circuit packages, and is thermally coupled to the first and second die. The cooling arrangement is to transfer heat generated by a first die of the first integrated circuit package and a second die of the second integrated circuit package. In some cases, structures comprising electrically conductive material (e.g., metal) are encapsulated by a molding compound or insulator, and extend between a first substrate of the first integrated circuit package and a second substrate of the second integrated circuit package.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Robert Sankman, MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Publication number: 20200226313
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Publication number: 20200211969
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20200186149
    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 11, 2020
    Applicant: Intel Corporation
    Inventors: Dheeraj Subbareddy, MD Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
  • Publication number: 20200176372
    Abstract: Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.
    Type: Application
    Filed: April 1, 2017
    Publication date: June 4, 2020
    Inventors: MD Altaf HOSSAIN, Dinesh SOMASEKHAR, Dheeraj SUBBAREDDY
  • Patent number: 10642946
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, Md Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Publication number: 20200133902
    Abstract: Systems and method include one or more die coupled to an interposer. The interposer includes interconnection circuitry configured to electrically connect the one or more die together via the interposer. The interposer also includes translation circuitry configured to translate communications as they pass through the interposer. For instance, in the interposer, the translation circuitry translates communications, in the interposer, from a first protocol of a first die of the one or more die to a second protocol of a second die of the one or more die.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy, Chee Hak Teh, MD Altaf Hossain
  • Patent number: 10601426
    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Dheeraj Subbareddy, Md Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
  • Publication number: 20200083890
    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 12, 2020
    Applicant: Intel Corporation
    Inventors: Dheeraj Subbareddy, MD Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
  • Publication number: 20200051901
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Application
    Filed: May 20, 2019
    Publication date: February 13, 2020
    Inventors: MD Altaf Hossain, Scott Gilbert
  • Publication number: 20190341349
    Abstract: A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.
    Type: Application
    Filed: March 29, 2017
    Publication date: November 7, 2019
    Inventors: MD Altaf Hossain, Kevin J Doran, Yu Amos Zhang, Zhiguo Qian
  • Publication number: 20190333854
    Abstract: An electronic chip, system, and method includes a power block including a power source configured to provide power to components of the electronic chip and a relay circuit coupled to the power source and a ground plane. The electronic chip further includes chip package having a first major side and a second major side, the power block secured to the second major side, the chip package comprising electrical connections, disposed on the second major side, to be secured with respect to a circuit board, and interconnect circuitry, electrically coupling the power block to ground, comprising a plurality of conductive layers, a conductive through hole, electrically connecting a first pair of the plurality of conductive layers, having a first width, and a via, electrically connecting a second pair of the plurality of conductive layers, having a second width less than the first width.
    Type: Application
    Filed: December 30, 2016
    Publication date: October 31, 2019
    Inventors: MD Altaf Hossain, Ankireddy Nalamalpu, Scott Gilbert, Jin Zhao