Patents by Inventor Md Altaf HOSSAIN

Md Altaf HOSSAIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200051901
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Application
    Filed: May 20, 2019
    Publication date: February 13, 2020
    Inventors: MD Altaf Hossain, Scott Gilbert
  • Publication number: 20190341349
    Abstract: A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.
    Type: Application
    Filed: March 29, 2017
    Publication date: November 7, 2019
    Inventors: MD Altaf Hossain, Kevin J Doran, Yu Amos Zhang, Zhiguo Qian
  • Publication number: 20190333854
    Abstract: An electronic chip, system, and method includes a power block including a power source configured to provide power to components of the electronic chip and a relay circuit coupled to the power source and a ground plane. The electronic chip further includes chip package having a first major side and a second major side, the power block secured to the second major side, the chip package comprising electrical connections, disposed on the second major side, to be secured with respect to a circuit board, and interconnect circuitry, electrically coupling the power block to ground, comprising a plurality of conductive layers, a conductive through hole, electrically connecting a first pair of the plurality of conductive layers, having a first width, and a via, electrically connecting a second pair of the plurality of conductive layers, having a second width less than the first width.
    Type: Application
    Filed: December 30, 2016
    Publication date: October 31, 2019
    Inventors: MD Altaf Hossain, Ankireddy Nalamalpu, Scott Gilbert, Jin Zhao
  • Publication number: 20190227590
    Abstract: A circuit system includes an interposer that has a first clock network and first and second integrated circuit dies that are mounted on the interposer. The first integrated circuit die includes a phase detector circuit, an adjustable delay circuit that generates a second clock signal in response to a first clock signal received from the first clock network, and a second clock network that generates a third clock signal in response to the second clock signal. The second integrated circuit die comprises a third clock network that generates a fourth clock signal in response to the first clock signal received from the first clock network. The phase detector circuit controls a delay provided by the adjustable delay circuit to the second clock signal based on a phase comparison between phases of the third and fourth clock signals.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 25, 2019
    Applicant: Intel Corporation
    Inventors: Jeffrey Chromczak, Chooi Pei Lim, Lai Guan Tang, Chee Hak Teh, MD Altaf Hossain, Dheeraj Subbareddy, Ankireddy Nalamalpu
  • Publication number: 20190230795
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 25, 2019
    Inventors: MD Altaf HOSSAIN, Scott A. GILBERT
  • Patent number: 10297542
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Publication number: 20190138680
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Publication number: 20190131268
    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.
    Type: Application
    Filed: June 29, 2018
    Publication date: May 2, 2019
    Applicant: Intel Corporation
    Inventors: MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 10278292
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Scott A. Gilbert
  • Publication number: 20190115293
    Abstract: An integrated circuit package may include a semiconductor die on a first side of the integrated circuit package, a first ball grid array (BGA) connection on the first side of the integrated circuit package, and a second BGA connection on a second side of the integrated circuit package. The integrated circuit package may include one or more traces that route data from the first BGA connection and the second BGA connection.
    Type: Application
    Filed: December 12, 2018
    Publication date: April 18, 2019
    Inventors: MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Dinesh Somasekhar
  • Publication number: 20190042505
    Abstract: An IC includes first, second, and third IOs, and a multiplexer that includes first and second inputs, and an output. The IC includes first and second transmitters respectively having an output coupled to the first IO and an output coupled to the second IO. A clock generator is coupled between the output and an input of the first transmitter and between the output and an input of the second transmitter. The first input may receive a clock signal generated by the first clock generator and the second clock input is coupled to the third IO and may receive a clock signal via the third IO element from another IC. An IC includes a programmable fabric, k*n wires coupled to and extending from the fabric, n TDMs, and n IO blocks. Each TDM includes k inputs coupled to k wires and an output coupled to one of the IO blocks.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Dheeraj Subbareddy, Ankireddy Nalamalpu, MD Altaf Hossain
  • Patent number: 9961769
    Abstract: The present disclosure relates to microelectronic substrates, such as interposers, motherboards, test platforms, and the like, that are fabricated to have overlapping connection zones, such that different microelectronic devices, such as microprocessors, chipsets, graphics processing devices, wireless devices, memory devices, application specific integrated circuits, and the like, may be alternately attached to the microelectronic substrates to form functional microelectronic packages.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: May 1, 2018
    Assignee: INTEL CORPORATION
    Inventors: Md Altaf Hossain, Cliff C. Lee, David W. Browning, Itai M. Pines, Brian P. Kelly
  • Publication number: 20180108605
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Application
    Filed: July 31, 2017
    Publication date: April 19, 2018
    Inventors: MD Altaf Hossain, Scott Gilbert
  • Patent number: 9940984
    Abstract: A shared command/address (C/A) bus for memory devices in a multi-channel configuration can enable reducing the number of pins and signal lines in a memory subsystem. In one embodiment, a memory controller includes hardware logic to generate commands to access a plurality of memory devices via a plurality of channels and input/output (I/O) circuitry to transmit command/address (C/A) information for the commands to the plurality of memory devices over a single C/A bus for the plurality of channels. In one embodiment, double-speed strobe signal lines can also enable reducing the number of pins and signal lines in a memory subsystem.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Nagi Aboulenein, Jayapratap Bharathan
  • Publication number: 20180090185
    Abstract: A shared command/address (C/A) bus for memory devices in a multi-channel configuration can enable reducing the number of pins and signal lines in a memory subsystem. In one embodiment, a memory controller includes hardware logic to generate commands to access a plurality of memory devices via a plurality of channels and input/output (I/O) circuitry to transmit command/address (C/A) information for the commands to the plurality of memory devices over a single C/A bus for the plurality of channels. In one embodiment, double-speed strobe signal lines can also enable reducing the number of pins and signal lines in a memory subsystem.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Inventors: MD Altaf HOSSAIN, Nagi ABOULENEIN, Jayapratap BHARATHAN
  • Publication number: 20180005972
    Abstract: Techniques and mechanisms for determining an accessibility of circuit functionality via interface structures of a microelectronic device. In an embodiment, a packaged microelectronic device includes a substrate having interconnect structures formed therein. The interconnect structures variously couple one or more integrated circuit (IC) dies of the packaged microelectronic device to respective conductors (or “contact lands”) at a side of the substrate. Access to some functionality of the one or more IC dies via certain ones the contact lands—the access during an operational mode of the packaged microelectronic device—may be selectively disabled based on testing which evaluates performance characteristics of the packaged microelectronic device. In another embodiment, some of the contact lands are covered with an insulator material to prevent deposition of solder on such contact lands.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Inventors: Md Altaf HOSSAIN, Cliff C. LEE
  • Patent number: 9799556
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: October 24, 2017
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Scott A. Gilbert
  • Patent number: 9721882
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Publication number: 20170141024
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Application
    Filed: January 30, 2017
    Publication date: May 18, 2017
    Inventors: MD Altaf Hossain, Scott Gilbert
  • Patent number: 9480162
    Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 25, 2016
    Assignee: INTEL CORPORATION
    Inventors: Md Altaf Hossain, Jin Zhao, John T. Vu