Patents by Inventor Mei-Sheng Zhou

Mei-Sheng Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8860142
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: October 14, 2014
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Debora Chyiu Hyia Poon, Alex K H See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 8754447
    Abstract: A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: June 17, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jin Ping Liu, Alex K H See, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 8716076
    Abstract: A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: May 6, 2014
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Jinping Liu, Alex K H See, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 8546873
    Abstract: A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 1, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jinping Liu, Hai Cong, Binbin Zhou, Alex Kh See, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 8415236
    Abstract: A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the first layer formation, a gas mixture comprising first and second source gases that function as growth components for forming the first layer and a reactant gas that functions as an etching component for controlling selectivity of the first layer growth is provided. The reactant gas is different from the first and second source gases and one of first and second source gases forms the first layer at a faster rate over the first exposed portion as compared to the second exposed portion and the other source gas exhibits an opposite behavior.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: April 9, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Han Guan Chew, Jinping Liu, Alex Kai Hung See, Mei Sheng Zhou
  • Patent number: 8394724
    Abstract: A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: March 12, 2013
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Hai Cong, Wei Loong Loh, Krishan Gopal, Xin Zhang, Mei Sheng Zhou, Pradeep Ramachandramurthy Yelehanka
  • Patent number: 8354347
    Abstract: A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: January 15, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jianhui Ye, Huang Liu, Alex K H See, Wei Lu, Chun Hui Low, Chim Seng Seet, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 8324011
    Abstract: The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: December 4, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Chyiu Hyia Poon, Alex See, Mei Sheng Zhou
  • Patent number: 8293544
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: October 23, 2012
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Debora Chyiu Hyia Poon, Alex Kh See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou, Liang Choo Hsia
  • Publication number: 20120012940
    Abstract: A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jinping LIU, Hai CONG, Binbin ZHOU, Alex KH SEE, Mei Sheng ZHOU, Liang Choo HSIA
  • Publication number: 20110281410
    Abstract: A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
    Type: Application
    Filed: July 26, 2011
    Publication date: November 17, 2011
    Inventors: JINPING LIU, Alex KH See, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 8058123
    Abstract: A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: November 15, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Jinping Liu, Hai Cong, Binbin Zhou, Alex K H See, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 8012839
    Abstract: A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: September 6, 2011
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jinping Liu, Alex K H See, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 7966142
    Abstract: A method for assessing metrology tool accuracy is described. Multi-variable regression is used to define the accuracy of a metrology tool such that the interaction between different measurement parameters is taken into account. A metrology tool under test (MTUT) and a reference metrology tool (RMT) are used to measure a set of test profiles. The MTUT measures the test profiles to generate a MTUT data set for a first measurement parameter. The RMT measures the test profiles to generate RMT data sets for the first measurement parameter, and at least a second measurement parameter. Multi-variable regression is then performed to generate a best-fit plane for the data sets. The coefficient of determination (R2 value) represents the accuracy index of the MTUT.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: June 21, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Wen Zhan Zhou, Zheng Zou, Jasper Goh, Mei Sheng Zhou
  • Patent number: 7960283
    Abstract: A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: June 14, 2011
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jeff Jianhui Ye, Huang Liu, Alex K H See, Wei Lu, Hai Cong, Hui Peng Koh, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 7902066
    Abstract: Interconnects for integrated circuits, such as damascene structures are formed using a hard mask. The hard mask is formed from, for example, high-k dielectric material such as hafnium oxide or other materials having high etch selectivity to the interconnect dielectric material. This enables a thin mask to etch vias and trenches in the interconnect dielectric layer, avoiding the problems associated with the use of thick mask layers, such as contact hole striations and small depth of focus, which can result in shorts or opens.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: March 8, 2011
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jian Hui Ye, Mei Sheng Zhou
  • Patent number: 7879732
    Abstract: A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching is provided by monitoring the removal of the endpoint detection layer. The endpoint detection layer is formed on a surface of an etching apparatus that is exposed to the same etching conditions as the thin film to be etched. The etching of the thin film is stopped when a predetermined amount of the endpoint detection layer has removed from the surface of the etching apparatus.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: February 1, 2011
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Xiang Hu, Hai Cong, Pradeep Yelehanka, Mei Sheng Zhou
  • Publication number: 20100308374
    Abstract: A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.
    Type: Application
    Filed: August 16, 2010
    Publication date: December 9, 2010
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jin Ping LIU, Alex KH SEE, Mei Sheng ZHOU, Liang Choo HSIA
  • Publication number: 20100267236
    Abstract: A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
    Type: Application
    Filed: June 28, 2010
    Publication date: October 21, 2010
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jianhui YE, Huang LIU, Alex KH SEE, Wei LU, Hai CONG, Hui Peng KOH, Mei Sheng ZHOU, Liang Choo HSIA
  • Patent number: 7776699
    Abstract: A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: August 17, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jin Ping Liu, Alex K H See, Mei Sheng Zhou, Liang Choo Hsia