Patents by Inventor Mei Yu

Mei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080251916
    Abstract: A novel UBM structure for improving the strength and performance of individual UBM layers in a UBM structure is disclosed. In one aspect, a UBM structure for disposal onto an electrically conductive element comprised of aluminum is disclosed. In one embodiment, the UBM structure comprises a tantalum layer disposed over the aluminum electrically conductive element, and a copper layer disposed over the tantalum layer, where the UBM structure is configured to receive a solder ball thereon.
    Type: Application
    Filed: April 12, 2007
    Publication date: October 16, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: CHIU SUNG CHENG, HSIU-MEI YU, CHIA-JEN CHENG, C.T. CHUANG, CHUN-YEN LO, LI-HSIN TSENG
  • Publication number: 20080157362
    Abstract: A method of manufacturing a solder bump structure on a semiconductor device is provided. In one embodiment, a semiconductor substrate is provided having a bonding pad and a passivation layer formed thereabove, the passivation layer having an opening therein exposing a portion of the bonding pad. A first under bump metallization (UBM) layer is formed over the bonding pad and the passivation layer. A mask layer is placed over the first UBM layer, the mask layer having an opening therein exposing a portion of the first UBM layer. The mask layer is thereafter etched to create a recess at the edges between the first UBM layer and the mask layer. A second UBM layer is deposited in the opening of the mask layer, the second UBM layer filling the recess and a portion of the opening of the mask layer.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Blenny Chang, Hsiu-Mei Yu, Gil Huang, Sung-Cheng Chiu
  • Patent number: 7378724
    Abstract: A method for providing a cavity structure on a semiconductor device is provided. The method of forming the cavity structure, which may be particularly useful in packaging an image sensor, includes forming a spacer layer over a substrate. The spacer layer may be formed from a photo-sensitive material which may be patterned using photolithography techniques to form cavity walls surrounding dies on the wafer. A packaging layer, such as a substantially transparent layer, may be placed directly upon the cavity walls prior to curing. In another embodiment, the cavity walls are cured, an adhesive is applied to a surface of the cavity walls, and the packaging layer placed upon the adhesive. Thereafter, the wafer may be diced and the individual dies may be packaged for use.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: May 27, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Mei Yu, Gil Huang, Chien-Tung Yu, Owen Chen
  • Patent number: 7364998
    Abstract: Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the passivation layer exposing portions of the contact pad. An under bump metallurgy (UBM) layer is deposited over the etched passivation layer and in the plurality of openings thereof to contact the contact pad. A photoresist layer is formed on the UBM layer and then patterned and etched to form at least one opening substantially overlying the contact pad. An electrically conductive material is deposited into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad. A portion of the remaining photoresist layer is removed. The UBM layer is etched using the electrically conductive material as a mask.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: April 29, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sung-Cheng Chiu, Hao-Yi Tsai, Hsiu-Mei Yu, Shih-Ming Chen, Shang-Yun Hou
  • Publication number: 20080044756
    Abstract: A method for removing dry film resist (DFR) from a fine pitch solder bump array on a semiconductor wafer provides for pre-soaking the wafer in a chemical bath then turbulently exposing the wafer to a chemical solution, both steps taking place in batch processing with the wafers processed in a vertical position. The wafers are then individually processed through a chemical spinning operation in which a chemical solution is dispensed from a spray nozzle while motion such as spinning is imparted the horizontally disposed wafer. The spin speed of the chemical spraying process may then be increased to accelerate physical removal of residue. Deionized water rinsing and spin-drying provide a solder bump array void of any DFR or other residuals.
    Type: Application
    Filed: August 17, 2006
    Publication date: February 21, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Min Tseng, Hsiu-Mei Yu, Wen-Hsiang Tseng, Chia-Jen Cheng, Y. L. Feng, Tung-Wen Hsieh
  • Publication number: 20080045499
    Abstract: The invention provides methods for determining whether an agent preferentially inhibits Presenilin-1-comprised ?-secretase relative to Presenilin-2-comprised ?-secretase. The invention also provides agents that preferentially inhibit Presenilin-1-comprised ?-secretase relative to Presenilin-2-comprised ?-secretase, pharmaceutical compositions comprising such compounds, and methods of treating Alzheimer's disease using such compounds. The invention also discloses that the N-terminal domain of presenilin-1 and -2 determines the difference in the production of A? by PS1-comprised and PS2-comprised gamma secretases. This finding identified the structural determinant for the observed difference in the production of A? by PS1-comprised and PS2-comprised gamma secretases. Such structural determinant was not identified before. This invention also provides a method for determining whether an agent specifically binds the N terminus of PS1.
    Type: Application
    Filed: February 6, 2007
    Publication date: February 21, 2008
    Inventors: Byron Zhao, Mei Yu, Guriqbal Basi
  • Patent number: 7187078
    Abstract: Solder bump structures for semiconductor device packaging is provided. In one embodiment, a solder bump structure comprises a semiconductor substrate, the substrate has at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad. At least one patterned and etched polymer layer is formed on a portion of the contact pad. At least one patterned and etched conductive metal layer is formed above the polymer layer and is aligned therewith. And at least one layer of solder material having a solder height is provided above the conductive metal layer, the layer of solder is aligned with the conductive metal layer, the layer of solder is thereafter reflown thereby creating a solder ball.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: March 6, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Tzu-Han Lin, Huei-Mei Yu, Chia-Jen Cheng, Chun-Yen Lo, Li-Hsin Tseng, Boe Su, Simon Lu
  • Publication number: 20070020906
    Abstract: Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the passivation layer exposing portions of the contact pad. An under bump metallurgy (UBM) layer is deposited over the etched passivation layer and in the plurality of openings thereof to contact the contact pad. A photoresist layer is formed on the UBM layer and then patterned and etched to form at least one opening substantially overlying the contact pad. An electrically conductive material is deposited into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad. A portion of the remaining photoresist layer is removed. The UBM layer is etched using the electrically conductive material as a mask.
    Type: Application
    Filed: July 21, 2005
    Publication date: January 25, 2007
    Inventors: Sung-Cheng Chiu, Hao-Yi Tsai, Hsiu-Mei Yu, Shih-Ming Chen, Shang-Yun Hou
  • Publication number: 20060246037
    Abstract: The present invention relates to methods for preventing cell death in a subject and the application of these methods for treating neurodegenerative diseases, such as Parkinson's disease, Alzheimer's disease, etc. In one embodiment of the invention, a method for preventing cell death may comprise effecting overexpression of an active form of ATF6 in the cell.
    Type: Application
    Filed: July 30, 2004
    Publication date: November 2, 2006
    Inventors: Bryon Zhao, Mei Yu
  • Patent number: 7122458
    Abstract: A method for fabricating a pad redistribution layer. First, at least one bonding pad exposed by a first passivation layer is provided. A diffusion barrier layer and a seed layer are then formed over the first passivation layer and the bonding pad. A patterned mask layer is then formed over the seed layer to expose a portion thereof over the bonding pad, and a metal layer is then formed thereon. A sacrificial layer is then formed over the substrate and the sacrificial layer over the patterned mask layer is removed. The conductive film exposed by the metal layer and the remaining sacrificial layer is then removed, leaving a pad redistribution layer for the bonding pad.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: October 17, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Jen Cheng, Hui-Mei Yu, Li-Hsin Tseng, Tzu-Han Lin, Ching-Chiang Wu, Chun-Yen Lo, Li-Chuan Huang, Boe Su
  • Publication number: 20060213804
    Abstract: A method for providing a cavity structure on a semiconductor device is provided. The method of forming the cavity structure, which may be particularly useful in packaging an image sensor, includes forming a spacer layer over a substrate. The spacer layer may be formed from a photo-sensitive material which may be patterned using photolithography techniques to form cavity walls surrounding dies on the wafer. A packaging layer, such as a substantially transparent layer, may be placed directly upon the cavity walls prior to curing. In another embodiment, the cavity walls are cured, an adhesive is applied to a surface of the cavity walls, and the packaging layer placed upon the adhesive. Thereafter, the wafer may be diced and the individual dies may be packaged for use.
    Type: Application
    Filed: June 24, 2005
    Publication date: September 28, 2006
    Inventors: Hsiu-Mei Yu, Gil Huang, Chien-Tung Yu, Owen Chen
  • Publication number: 20060113640
    Abstract: In one embodiment, the disclosure relates to a method and apparatus for surface recovery of a polymer insulation layer through implantation. The method includes providing a substrate having thereon a conductive pad and an insulation layer, optionally processing the conductive pad to remove oxide layer formed on the conductive pad and conducting ion implantation to recover dielectric properties of the insulation layer.
    Type: Application
    Filed: November 29, 2004
    Publication date: June 1, 2006
    Inventors: Hsiu-Mei Yu, Ken-Shen Chou, Shun-Liang Hsu
  • Publication number: 20060105560
    Abstract: A method for forming solder bumps (or solder balls after reflow) of improved height and reliability is provided. In one embodiment, a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad is provided. A layer of under bump metal (UBM) is formed above the passivation layer and the contact pad. A first patterned and etched photoresist layer is provided above the UBM layer, the first patterned and etched photoresist layer defining at least one first opening therein. A second patterned and etched photoresist layer is provided above the first patterned and etched photoresist layer, the second patterned and etched photoresist layer defining at least one second opening therein, the second opening being wider than the first opening. A solder material is filled in the at least one first opening and substantially filled in the at least one second opening.
    Type: Application
    Filed: November 16, 2004
    Publication date: May 18, 2006
    Inventors: Li-Hsin Tseng, Gil Huang, Huei-Mei Yu, Chia-Jen Cheng, Ken Sun, Chien-Tung Yu, Blenny Chang, Chih Chan, Jian-Wen Luo, Owen Chen
  • Publication number: 20060055035
    Abstract: Solder bump structures for semiconductor device packaging is provided. In one embodiment, a solder bump structure comprises a semiconductor substrate, the substrate has at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad. At least one patterned and etched polymer layer is formed on a portion of the contact pad. At least one patterned and etched conductive metal layer is formed above the polymer layer and is aligned therewith. And at least one layer of solder material having a solder height is provided above the conductive metal layer, the layer of solder is aligned with the conductive metal layer, the layer of solder is thereafter reflown thereby creating a solder ball.
    Type: Application
    Filed: September 13, 2004
    Publication date: March 16, 2006
    Inventors: Tzu-Han Lin, Huei-Mei Yu, Chia-Jen Cheng, Chun-Yen Lo, Li-Hsin Tseng, Boe Su, Simon Lu
  • Publication number: 20060019480
    Abstract: A method for fabricating a pad redistribution layer. First, at least one bonding pad exposed by a first passivation layer is provided. A diffusion barrier layer and a seed layer are then formed over the first passivation layer and the bonding pad. A patterned mask layer is then formed over the seed layer to expose a portion thereof over the bonding pad, and a metal layer is then formed thereon. A sacrificial layer is then formed over the substrate and the sacrificial layer over the patterned mask layer is removed. The conductive film exposed by the metal layer and the remaining sacrificial layer is then removed, leaving a pad redistribution layer for the bonding pad.
    Type: Application
    Filed: July 22, 2004
    Publication date: January 26, 2006
    Inventors: Chia-Jen Cheng, Hui-Mei Yu, Li-Hsin Tseng, Tzu-Han Lin, Ching-Chiang Wu, Chun-Yen Lo, Li-Chuan Huang, Boe Su
  • Patent number: 6941957
    Abstract: A method including the step of providing a substrate having a contact pad, and an under bump metallurgy overlying the contact pad, and a photoresist layer overlying the under bump metallurgy, and wherein the photoresist layer has an opening defined therein down to the under bump metallurgy and aligned with the contact pad. Pretreating the substrate with the first wetting solution prior to plating a first seed layer over the under bump metallurgy. Thereafter, plating a first seed layer is plated onto the under bump metallurgy.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: September 13, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Kuo-Feng Chen, Hsiu-Mei Yu, Charles Tseng, Ta-Yang Lin
  • Patent number: 6784002
    Abstract: A wafer bumping method comprising the following steps of. A wafer having fields is provided. The wafer having at least one wafer identification character formed thereon within one or more of the fields. A dry film resist is formed over the wafer. Portions of the dry film resist are selectively exposed field by field using a mask whereby the mask is shifted over the one or more fields containing the at least one wafer identification character so that the one or more fields containing the at least one wafer identification character is double exposed after the mask shift so that all of the one or more fields containing the at least one wafer identification character is completely exposed. The selectively exposed dry film resist is developed to remove the non-exposed portions of the dry film resist.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: August 31, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hui-Peng Wang, Kuo-Wei Lin, Hwei-Mei Yu, Ta-Yang Lin, Charles Tseng
  • Patent number: 6696356
    Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip without producing metal ribbon residue. The method includes the step of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A photoresist layer is deposited over the under bump metallurgy. The photoresist layer is a dry film photoresist. The photoresist layer is patterned to provide an opening in the photoresist layers down to the under bump metallurgy and aligned with the contact pad. Additional energy is applied to the photoresist layer to improve the adhesion of the photoresist layer to the under bump metallurgy. An electrically conductive material is deposited into the opening formed in the photoresist layers and overlying the under bump metallurgy and aligned with contact pad.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: February 24, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hsin Tseng, Hsiu-Mei Yu, Ta-Yang Lin, Fang-Chung Liu, Kai-Ming Ching, Tung-Heng Shie
  • Patent number: 6688694
    Abstract: A chair comprises a seat frame and a backrest frame. A first connecting member is provided on each of two lateral sides of the seat frame. A second connecting member is provided on each of two lateral sides of the backrest frame. Each second connecting member is pivotally connected with an associated first connecting member. The inclination angle of the backrest frame relative to said seat frame is adjustable. A safety device includes a frame fixed to one of the second connecting member and a pin extending through the frame and including an end located on a path of the associated first connecting member, thereby restraining a maximum inclination angle of the backrest frame relative to the seat frame. The safety pin is movable away from the path of the associated first connecting member, allowing the backrest frame to be moved to a position aligned with the seat frame.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: February 10, 2004
    Inventor: Wei-mei Yu
  • Publication number: 20040013804
    Abstract: A method including the step of providing a substrate having a contact pad, and an under bump metallurgy overlying the contact pad, and a photoresist layer overlying the under bump metallurgy, and wherein the photoresist layer has an opening defined therein down to the under bump metallurgy and aligned with the contact pad. Pretreating the substrate with the first wetting solution prior to plating a first seed layer over the under bump metallurgy. Thereafter, plating a first seed layer is plated onto the under bump metallurgy.
    Type: Application
    Filed: July 16, 2003
    Publication date: January 22, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Feng Chen, Hsiu-Mei Yu, Charles Tseng, Ta-Yang Lin