Patents by Inventor Mei Yu

Mei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110315351
    Abstract: A vapor chamber having a composite supporting structure includes a flat sealed casing; a wick structure, a working fluid and a composite supporting structure. The composite supporting structure has a waved supporting rack and at least one supporting pillar. The waved supporting rack is configured to support upper and lower inner walls of the flat sealed casing. The waved supporting rack has plural separated channels for allowing vapor of the working fluid to flow through. Both ends of the at least one supporting pillar are respectively connected to the flat sealed casing or the wick structure. With this arrangement, compressive strength and tensile strength of the vapor chamber can be increased simultaneously without obstructing the circulation of liquid/vapor phases of the working fluid and reducing the thermal-conducting efficiency thereof.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Inventors: George Anthony. Meyer, IV, Chien-Hung Sun, Chieh-Ping Chen, Yung-Tai Lu, Te-Hsuan Chin, Mei-Yu Chen
  • Patent number: 8048778
    Abstract: An embodiment of the disclosure includes a method of dicing a semiconductor structure. A device layer on a semiconductor substrate is provided. The device layer has a first chip region and a second chip region. A scribe line region is between the first chip region and the second chip region. A protective layer is formed over the device layer thereby over the semiconductor substrate. The protective layer on the scribe line region is laser sawn to form a notch. The notch extends into the semiconductor substrate and the protective layer is formed to cover a portion of the notch. A mechanically sawing is performed through the portion of the protective layer and the substrate to separate the first chip region and the second chip region.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: November 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Yu Ku, Hsiu-Mei Yu, Chun-Ying Lin, Young-Chang Lien, Sheng-Hsiang Chiu, Ta-Jen Yu
  • Publication number: 20110257184
    Abstract: A method of treating SHP-2 phosphatase associated diseases in a subject includes administering a SHP-2 inhibitor to the subject.
    Type: Application
    Filed: November 15, 2010
    Publication date: October 20, 2011
    Inventors: Cheng-Kui Qu, Wen-Mei Yu, Olgun Guvench, Alexander D. Mackerell, JR.
  • Publication number: 20110241179
    Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
    Type: Application
    Filed: June 20, 2011
    Publication date: October 6, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chang Hsieh, Hung-Lin Chen, Hsiu-Mei Yu, Chin Kun Lan, Dong-Lung Lee
  • Publication number: 20110182455
    Abstract: An acoustic system includes a receiver or microphone, a tube, a barrier, and an equalization device. The receiver is capable of outputting an audio signal. The tube is in connection with the receiver and the audio signal travels along a length of the tube. The barrier is fitted along the tube and the barrier prevents moisture from passing along the tube toward the receiver. The barrier causes an amount of damping to the audio signal. The equalization device is in connection with the receiver and the equalization device counteracts the damping by the barrier. The barrier is configured to have a submersion rating greater than or equal to 7 IP.
    Type: Application
    Filed: January 19, 2011
    Publication date: July 28, 2011
    Inventors: Timothy K. Wickstrom, William J. Ballad, Mei-Yu Lin, Ying-Tzu Chan, Jen Nan Feng
  • Patent number: 7968431
    Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: June 28, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chang Hsieh, Hung-Lin Chen, Hsiu-Mei Yu, Chin Kun Lan, Dong-Lung Lee
  • Publication number: 20110070481
    Abstract: The present invention provides a protective material, which includes an acidic material and an absorbent additive. An alkaline electrolyte will be neutralized by the acidic material, and water produced from the neutralization reaction of the acidic material and the alkaline electrolyte will be absorbed by the absorbent additive. In addition, the present invention also discloses an energy storage module using the same.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 24, 2011
    Applicant: DELTA ELECTRONICS, INC.
    Inventors: Rong-Chang LIANG, Chieh-Lin Hsing, Hsiao-Wen Huang, Mei-Yu Yeh
  • Patent number: 7863742
    Abstract: An integrated circuit structure includes a passivation layer; a via opening in the passivation layer; a copper-containing via in the via opening; a polymer layer over the passivation layer, wherein the polymer layer comprises an aperture, and wherein the copper-containing via is exposed through the aperture; a post-passivation interconnect (PPI) line over the polymer layer, wherein the PPI line extends into the aperture and physically contacts the copper-via opening; and an under-bump metallurgy (UBM) over and electrically connected to the PPI line.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: January 4, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Mei Yu, Tjandra Winata Karta, Daniel Yang, Shih-Ming Chen, Chia-Jen Cheng
  • Publication number: 20100308499
    Abstract: A method for forming a composite laminate includes: providing an upper die and a lower die; disposing the composite laminate over a die cavity of the lower die, and lowering the upper die onto the composite laminate and thereafter into the die cavity so as to hot press the composite laminate; folding inwardly a marginal end of the composite laminate that extends outwardly of the die cavity; removing the lower die from the upper die; and removing the upper die from the hot-pressed composite laminate.
    Type: Application
    Filed: October 13, 2009
    Publication date: December 9, 2010
    Applicant: ADVANCED INTERNATIONAL MULTITECH CO., LTD.
    Inventors: Mei-Yu Chen, Chang-Hung Tsai
  • Publication number: 20100309191
    Abstract: A shift register of an LCD device operates based on two clock signals and maintains the gate voltage of an output transistor switch using two pull-down transistor switches. The gate voltages of the pull-down transistor switches are switched periodically between the high and low level of the clock signals. During the output period, the transistor switches have negative gate-source voltages so as to reduce leakage.
    Type: Application
    Filed: November 18, 2009
    Publication date: December 9, 2010
    Inventors: Je-Hao Hsu, Wen-Pin Chen, Chiu-Mei Yu, Lee-Hsun Chang
  • Publication number: 20100222458
    Abstract: The present invention provides the compositions and processing methods of an environmental-friendly, multiple-effect powder. The compositions of environmental-friendly, multiple-effect powder include: cement, discarded PCB powder, resin, wasted coating powder and volcano mud powder. The environmental-friendly, multiple-effect powder of the present invention can also be widely applied to civil works as a coating/filling material or other composite building materials due to its advantages such as good thermal insulation, noise absorption, water-proofing, resistance to mildew, rustiness and acid/alkali, excellent robustness and moisture retention with better industrial and economic benefits.
    Type: Application
    Filed: March 2, 2009
    Publication date: September 2, 2010
    Inventors: Wu-Tian Wang, Wu-Ching Wang, Mei-Yu Huang Wang, Shiau-Ming Wang, Shiau-Hau Wang, Shi-Cheng Huang, Chen Hong, Teng-Ki Lin
  • Patent number: 7781140
    Abstract: A method for removing dry film resist (DFR) from a fine pitch solder bump array on a semiconductor wafer provides for pre-soaking the wafer in a chemical bath then turbulently exposing the wafer to a chemical solution, both steps taking place in batch processing with the wafers processed in a vertical position. The wafers are then individually processed through a chemical spinning operation in which a chemical solution is dispensed from a spray nozzle while motion such as spinning is imparted the horizontally disposed wafer. The spin speed of the chemical spraying process may then be increased to accelerate physical removal of residue. Deionized water rinsing and spin-drying provide a solder bump array void of any DFR or other residuals.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: August 24, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Min Tseng, Hsiu-Mei Yu, Wen-Hsiang Tseng, Chia-Jen Cheng, Yu-Lung Feng, Tung-Wen Hsieh
  • Publication number: 20100201902
    Abstract: In a display device and a repairing method therefor, the display device includes a gate line and two gate-on-array circuits arranged at two sides thereof. Each of the gate-on-array circuits includes a stage coupled to the gate line. Each the stage includes a transistor and a repair circuit. The first source/drain electrode of the transistor is coupled to the gate line, and the second source/drain electrode of the transistor is coupled to receive a clock pulse signal. The repair circuit includes a first terminal coupled to the gate electrode of the transistor, a second terminal coupled to a predetermined potential, and at least one control terminal adapted to receive at least one repair signal to pull the potential on the gate electrode of the transistor to the predetermined potential. The transistor maintains at off-state when the at least one repair signal is supplied to the repair circuit.
    Type: Application
    Filed: September 3, 2009
    Publication date: August 12, 2010
    Inventors: Je-Hao HSU, Wen-Pin Chen, Chiu-Mei Yu, Lee-Hsun Chang
  • Publication number: 20100169852
    Abstract: A system and method for detecting one or more winding paths for patterns on a reticle for the manufacture of semiconductor integrated circuits. A method for detecting invalid winding path in a layout design. The method includes the step of obtaining a first winding path parameter and a second winding path parameter. The method includes defining a first plurality of reticle patterns in accordance with the first winding path parameter and the second winding path parameter. The first winding path parameter has a first value. The first plurality of reticle patterns is associated with the least one winding path. The method additionally includes defining a second plurality of reticle patterns in accordance with the second winding path parameter and the second winding path parameter. The first winding path parameter has a second value. The second plurality of reticle patterns is associated with the at least one winding path.
    Type: Application
    Filed: December 29, 2009
    Publication date: July 1, 2010
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Kuei Mei Yu
  • Patent number: 7714414
    Abstract: In one embodiment, the disclosure relates to a method and apparatus for surface recovery of a polymer insulation layer through implantation. The method includes providing a substrate having thereon a conductive pad and an insulation layer, optionally processing the conductive pad to remove oxide layer formed on the conductive pad and conducting ion implantation to recover dielectric properties of the insulation layer.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: May 11, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiu-Mei Yu, Ken-Shen Chou, Shun-Liang Hsu
  • Publication number: 20100085083
    Abstract: A gate driving circuit having a low leakage current control mechanism is disclosed for providing a plurality of gate signals forwarded to a plurality of gate lines respectively. The gate driving circuit includes a plurality of shift registers. Each shift register includes a driving unit, an energy store unit, a buffer unit, a voltage regulation unit, and a control unit. The driving unit generates a gate signal based on a driving control voltage and a first clock. The buffer unit functions to receive a start pulse signal. The energy store unit provides the driving control voltage through performing a charging process based on the start pulse signal. The control unit generates a control signal based on the first clock and a second clock having a phase opposite to the first clock. The voltage regulation unit regulates the driving control voltage based on the control signal.
    Type: Application
    Filed: December 9, 2008
    Publication date: April 8, 2010
    Inventors: Lee-Hsun Chang, Wen-Pin Chen, Je-Hao Hsu, Chiu-Mei Yu
  • Publication number: 20100079443
    Abstract: An apparatus, a shifter register unit, a liquid crystal display device and a method for eliminating afterimage are provided herein, which merely utilize a high voltage source delay discharging phenomenon oriented from a powered-off power device to lead any two of a plurality of existing signal sources employed by the shift register unit to reach a high level used for controlling of charge and discharge of a discharge switching unit corresponding to a pixel unit. Therefore, a power-off afterimage problem could be improved and a signal reset function for power-on also can be achieved.
    Type: Application
    Filed: September 1, 2009
    Publication date: April 1, 2010
    Applicant: AU Optronics Corp.
    Inventors: Lee-Hsun Chang, Chiu-Mei Yu, Wen-Pin Chen, Je-Hao Hsu
  • Publication number: 20100013059
    Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
    Type: Application
    Filed: July 15, 2008
    Publication date: January 21, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chang Hsieh, Hung-Lin Chen, Hsiu-Mei Yu, Chin Kun Lan, Dong-Lung Lee
  • Publication number: 20090256831
    Abstract: A display apparatus and a circuit reparation method thereof are provided. The display apparatus comprises a control module, a first gate on array (GOA) circuit, a second GOA circuit, and a variable voltage source. The control module generates at least one control signal. The first GOA circuit is electrically connected to the control module according to a first leading wire in advance. The second GOA circuit is electrically connected to the control module according to a second leading wire in advance. The variable voltage source provides a predetermined voltage level. When the first GOA circuit is disabled, the first GOA circuit and the control module are adjusted to be electrically disconnected, and the first leading wire is electrically connected to the variable voltage source. The display apparatus is operated in response to the control signal and the predetermined voltage level.
    Type: Application
    Filed: August 13, 2008
    Publication date: October 15, 2009
    Applicant: AU OPTRONICS CORP.
    Inventors: Je-Hao Hsu, Lee-Hsun Chang, Wen-Pin Chen, Chiu Mei Yu
  • Publication number: 20090168985
    Abstract: A communication system provides for an Internet Protocol Multimedia Subsystem (IMS)-based three way call. A mobile station (MS) that receives an invitation to participate in a call determines to switch the call to a three way call. The MS conveys a request to an IMS network to switch the call to a conference call. An IMS network server receives the request, determines a unique identifier for the conference call, and provides the conference call identifier to the MS via one or more of a Session Initiation Protocol Refer message, Message message, and Notify message. In response to receiving the conference call identifier, the MS dials into the conference call and requests that the call originator also dial in. The IMS network server then requests that the call originator dial in, and the call originator does so in response to the request.
    Type: Application
    Filed: October 27, 2008
    Publication date: July 2, 2009
    Applicant: MOTOROLA, INC.
    Inventors: Mei Yu, Thomas G. Hallin, Anjum Jeelani, Srinidhi N