Abstract: Systems and methods are provided for a secondary authentication of a memory module. A nonce key is written to a nonce register of a register array on the memory module, the nonce register being accessible over two different interfaces. In various embodiments, the nonce key may be generated by a management system of the computing platform after performing one or more authentication processes for a memory module over a management interface. Authentication information for use in performing authentication can be stored in an identification component on the memory module. If authentication is successful, the management system can generate the nonce key and write it to the nonce register. Upon receiving a request to access an address, a memory controller can read the nonce register of the memory module at the requested address and compare the nonce key to an identifier included in the request.

Abstract: Encrypted memory access using page table attributes is disclosed. One example is a memory system including a memory controller at a memory interface. The memory controller includes an encryptor to control a plurality of memory access keys respectively associated with memory regions, where each memory region is allocated to a respective client, and an access manager to receive an access request from a client, the access request including a client access key to access a memory element. The access manager looks up a memory access key from a page table attribute associated with a physical address of the memory element, and determines if the access request is valid by comparing the client access key with the memory access key associated with the memory region that includes the memory element. Based on the determination and a mode of operation, the access manager provides a response to the access request.

Abstract: A printed circuit board includes a top conducting layer, an escaping layer, one or more first reference layers interposed between the top conducting layer and the escaping layer, and a second reference layer disposed under the escaping layer. The top conducting layer includes two connecting pads for receiving a pair of differential signals. A pair of vias are provided to extend vertically to penetrate the one or more first reference layers, the escaping layer, and the second reference layer. The vias connects the top conducting layer with the escaping layer. Each of the one or more first reference layers includes a continuous via void surrounding the pair of vias. The second reference layer includes two round via voids each surrounding one of the vias. The second reference layer includes a conductive film disposed between the two round via voids.

Abstract: Example implementations relate to tracking memory unit errors on a memory device. In example implementations, a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value.

Abstract: In some examples, a device includes a memory controller to, during a power-on process of the device: read encrypted data from a nonvolatile memory, decrypt, using a first key, the encrypted data to produce decrypted data, encrypt, using a second key different from the first key produced as part of rekeying, the decrypted data to produce new encrypted data, and write the new encrypted data to the nonvolatile memory. A power-on code is to prevent booting of the device until all data in the nonvolatile memory has been encrypted using the second key.

Abstract: A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.

Abstract: Electrical contacts described herein reduce electromagnetic interference and electrical resistance for circuits that handle high-frequency electrical currents. An electrical contact described herein comprises a base portion. The length of the base portion is greater than the width of the base portion. An indentation in a first side of the base portion is opposite an indentation on a second side of the base portion. The width of the protrusion is less than the width of the base portion. The protrusion is configured to be placed against a second electrical contact to allow an electrical current to flow through the electrical contact. The position of the protrusion relative to the second electrical contact and the geometry of the protrusion can eliminate stubs that cause electromagnetic interference and increase the area of contact between the first electrical contact and the second electrical contact.

Abstract: Electrical contacts described herein reduce electromagnetic interference and electrical resistance for circuits that handle high-frequency electrical currents. An electrical contact described herein comprises a base portion. The length of the base portion is greater than the width of the base portion. An indentation in a first side of the base portion is opposite an indentation on a second side of the base portion. The width of the protrusion is less than the width of the base portion. The protrusion is configured to be placed against a second electrical contact to allow an electrical current to flow through the electrical contact. The position of the protrusion relative to the second electrical contact and the geometry of the protrusion can eliminate stubs that cause electromagnetic interference and increase the area of contact between the first electrical contact and the second electrical contact.

Abstract: A device including a controller coupled to a primary medium including data provided by a processor, the controller configured to initiate an emergency backup for the primary medium, is provided. The device also includes a secondary medium coupled to the controller, and configured to store at least a portion of the data from the primary medium in the emergency backup. The device also includes an interface configured to provide to the controller, through a main power interface for the primary medium: an emergency backup signal to start the emergency backup, and a power to the primary medium during the emergency backup. A system including the device and a non-transitory medium with instructions to use the device in an emergency backup process are also provided.

Abstract: A method as disclosed herein includes writing a data portion in a selected block of a primary medium. In some embodiments, the method includes determining a data authentication value for the selected block, identifying an emergency signal for the primary medium, and transferring the data portion and the data authentication value to a secondary medium when the emergency signal is asserted by a controller. In some embodiments, the method includes reading the data portion from the secondary medium, determining whether the data portion has been compromised in the secondary medium based on the data authentication value, and notifying a processor, with the controller, that the data portion has been compromised in the secondary medium.

Abstract: One example includes a system. The system includes an error injection system. The error injection system includes an error injector to store a programmable control structure to define a memory error. The error injector being further used to inject the memory error into a respective one of a plurality of memory storage elements associated with a memory system at a predetermined address via an address controller and to determine if the memory error at the predetermined address associated with the respective one of the plurality of memory storage elements is corrected via error-correcting code (ECC) memory associated with the memory system.

Abstract: A synchronous differential memory interconnect may include a bidirectional differential data signal bus, a unidirectional differential command and address bus, and a differential clock signal. Memory read and write data may be transmitted over the data signal bus in a serial fashion.

Abstract: In one example in accordance with the present disclosure, a system for backup of a physical memory region of volatile memory. The system may include: a non-volatile memory, a volatile memory, at least one processor to: execute an application that indicates a virtual memory region stored in the volatile memory, wherein the virtual memory region is associated with an application, determine a corresponding physical memory region of the volatile memory for backup based on the indicated virtual memory region, and at least one memory controller to: receive a backup signal for the physical memory region of the volatile memory, and responsive to receiving the backup signal, backup up the physical memory region of the volatile memory to a memory region of the non-volatile memory.

Abstract: Systems and methods are provided for multi-layer data protection for memory devices. The method comprises receive data, generate an authentication code based on the data, encrypt the data and the authentication code, and write the encrypted data and authentication code to a memory device.

Abstract: Examples herein disclose selecting a row of data among multiple rows of data for validation of a repair to the selected row of data. The examples here disclose validating the repair to the selected row of data.

Abstract: A thermal management assembly in accordance with one example may include a first thermal management member that includes a first main region that is continuous, a first connection region that is discontinuous, and a first top side. The thermal management assembly may also include a second thermal management member that includes a second main region, a second connection region, and a second top side. The second main region and the second connection region are continuous. The thermal management assembly may further include a connection member to couple the first thermal management member and the second thermal management member to a memory device via the first connection region and the second connection region. The first top side and the second top side are substantially level with a top side of the memory device in a horizontal direction when the first thermal management member and the second thermal management member are coupled to the memory device.

Abstract: Examples disclosed herein relate to fabric cable emulation. Some examples disclosed herein include determining connection data associated with a connection between a fabric interface of a cluster node in a fabric cluster and a fabric switch. Based on the determined connection data, configuration parameters for the connection may be calculated and stored in a memory device on the cluster node. An interface signal may be asserted to the fabric interface of the cluster node after the calculated configuration parameters are stored to indicate that the cluster node is available in the fabric cluster.

Abstract: The present disclosure discloses an expansion bus device that is communicatively coupled to a plurality of input-output devices. The expansion bus device includes a plurality of input-output slots, via which the plurality of input-output devices are coupled to the expansion bus device. The expansion bus device also includes a retimer switch communicatively connected to each of the plurality of input-output slots. The retimer switch supports switching between the plurality of input-output slots.

Abstract: One of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) may be repurposed to an address input. One of a plurality of memory ranks of the LRDIMM may be selected based on a remainder of the plurality of chip select inputs. The repurposed chip select input may be used to support non-binary rank multiplication of the LRDIMM.

Abstract: In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.