Abstract: A technique includes monitoring activation rates of a plurality of memory locations associated with a plurality of memory addresses and regulating the activation rates. The regulating includes selectively updating a cache with the memory addresses based on the activation rates.

Abstract: A computing system can include a processor and a memory. The computing system can also include a memory controller to interface between the processor and the memory. The memory controller coalesces requests to access a memory row to form a single request to access the memory row.

Abstract: A technique includes during in-service use of a memory package in a computer system, using a first interface to access a defective address memory of the memory package. The defective address memory is accessible by a manufacturer of the memory package prior to the in-service use using a second interface of the memory package other than the first interface. In connection with the in-service use of the memory package, the memory package is repair, a repair that includes storing a defective address in the defective address memory to change an address mapping for at least one cell of the storage array.

Abstract: DIMM seating errors may be detected. An example detection method includes determining whether a training error has occurred for a number of dynamic random access memories (DRAMs) of a DIMM. The Example method includes identifying a location for each of the DRAMs. The example method includes determining whether a seating error has occurred based on the training error, the number, and the location of the DRAMs.

Abstract: An apparatus includes a memory module, which includes a memory array. The memory array includes rows of memory and columns of memory. The apparatus also includes at least one row of memory not in the memory array and a register. The register includes an address space and a row/column indicator. The apparatus also includes row selection logic to select the at least one row to be activated if the address from an address bus equals the register value and if the row/column indicator indicates row.

Abstract: An error test routine tests for a type of memory error by changing a content of a memory module. A memory handling procedure isolates the memory error in response to a positive outcome of the error test routine. The error test routine and memory handling procedure are to be performed at runtime transparent to an operating system. Information corresponding to isolating the memory error is stored.

Abstract: The present disclosure describes, in one example, a dual inline memory module socket. The dual inline memory module socket includes a base to receive a memory module. The base further comprises a first detection pin and a second detection pin. A latch may be coupled to the base and is to electrically couple the first detection pin to the second detection pin in a dosed position to enable a determination that the memory module is properly seated.

Abstract: A nonvolatile memory (10) is partitioned into bank groups (24) based upon a write-to-read latency of the nonvolatile memory (10).

Abstract: A technique includes delaying bus activity targeting a memory device and indicating a command for the memory device to allow time for the memory device to complete processing the command. The delaying of the bus activity includes selectively generating an error signal on a memory bus.

Abstract: Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate.

Abstract: An error test routine is to test for a type of memory error by changing a content of a memory module. A memory handling procedure is to isolate the memory error in response to a positive outcome of the error test routine. The error test routine and memory handling procedure is to be performed at runtime transparent to an operating system. Information corresponding to isolating the memory error is stored.

Abstract: A system in some embodiments includes a system having a memory module having a first board comprising a first plurality of memory receptacles configured to support a first plurality of in-line memory modules in an overlapping relationship with a second plurality of in-line memory modules disposed on a second board. Further, a system in some embodiments includes rotating first and second memory boards into a parallel configuration via a hinge coupling the first and second memory boards, and inserting the first and second memory boards into first and second board connectors simultaneously.

Abstract: Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate.

Abstract: A voltage regulator is provided that includes current sense circuitry configured to detect an amount of current provided to a load, a voltage controlled oscillator configured to output a clock signal with a constant duty cycle at a frequency that varies in dependence on the amount of current detected by current sense circuitry, and regulator circuitry configured to provide a regulated voltage to the load using the clock signal.

Abstract: Systems and methods for improving performance of a rentable fabric are disclosed. In an exemplary embodiment a system may comprise a plurality of compute nodes, a routable fabric, and a plurality of chipsets connected by the routable fabric to the plurality of compute nodes. The chipsets have range registers dynamically directing traffic from any device to any of the plurality of compute nodes over the routable fabric.

Abstract: A system in some embodiments includes a system having a memory module having a first board comprising a first plurality of memory receptacles configured to support a first plurality of in-line memory modules in an overlapping relationship with a second plurality of in-line memory modules disposed on a second board. Further, a method in some embodiments includes rotating first and second memory boards into a parallel configuration via a hinge coupling the first and second memory boards, and inserting the first and second memory boards into first and second board connectors simultaneously.

Abstract: Systems and methods for improving performance of a rentable fabric are disclosed. In an exemplary embodiment a system may comprise a plurality of compute nodes, a routable fabric, and a plurality of chipsets connected by the routable fabric to the plurality of compute nodes. The chipsets have range registers dynamically directing traffic from any device to any of the plurality of compute nodes over the routable fabric.