Abstract: Example implementations relate to tracking memory unit errors on a memory device. In example implementations. a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value.

Abstract: A dual in-line memory module (DIMM) connector can include a double data rate fourth generation (DDR4) DIMM connector to connect to a DIMM via a lowest notch of the DIMM relative to an electronic component on which the DIMM is located.

Abstract: A table may include first and second row addresses that are adjacent an activated row address. A first counter of the first row address may be incremented if the activated row address is not included in the table. A second counter of the second row address may also be incremented if the activated row address is not included in the table. The first row address may be refreshed if the first counter exceeds a counter threshold. The second row address may be refreshed if the second counter exceeds the counter threshold.

Abstract: Example implementations relate to dynamic random-access memory (DRAM) row sparing. In example implementations, utilization of a failed row of a DRAM device may be excluded. A fuse in the DRAM device may be blown to replace the failed row with a spare row. The fuse may be blown during runtime operation of the DRAM device. Error-correcting code (ECC) may be used to correct erroneous data from the failed row while the fuse is being blown. Accesses of the failed row may be redirected to the spare row after the fuse is blown.

Abstract: A method is described in which a functional region on a printed circuit board (PCB) is defined, a regional circuit design to be inserted into the functional region on the PCB is selected, and the regional circuit design is pasted into the functional region.

Abstract: Examples herein disclose selecting a row of data among multiple rows of data for validation of a repair to the selected row of data. The examples here disclose validating the repair to the selected row of data.

Abstract: A memory module connector (100) is described herein. The memory module connector (100) comprises a plurality of connector pins (102) distributed into a plurality of columns (104). The plurality of connector pins (102) further comprises a plurality of ground pins (106) for providing electrical ground to the memory module connector (100) and a plurality of signal pins (108) for carrying data signals across the memory module connector (100). Further, for each signal pin (108) provided in a column (104), each connector pin (102) adjacent to the signal pin (108) in an adjacent column (104) is a ground pin (106).

Abstract: A thermal management assembly in accordance with one example may include a first thermal management member that includes a first main region that is continuous, a first connection region that is discontinuous, and a first top side. The thermal management assembly may also include a second thermal management member that includes a second main region, a second connection region, and a second top side. The second main region and the second connection region are continuous. The thermal management assembly may further include a connection member to couple the first thermal management member and the second thermal management member to a memory device via the first connection region and the second connection region. The first top side and the second top side are substantially level with a top side of the memory device in a horizontal direction when the first thermal management member and the second thermal management member are coupled to the memory device.

Abstract: A system can include a memory circuit having a first signal via, a first signal return via, and at least one second signal return via located closer to the control signal via than the first signal return via.

Abstract: One of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) may be repurposed to an address input. One of a plurality of memory ranks of the LRDIMM may be selected based on a remainder of the plurality of chip select inputs. The repurposed chip select input may be used to support non-binary rank multiplication of the LRDIMM.

Abstract: An example device includes a first error corrector to perform platform error correction based on a stride length. A memory includes a second error corrector that is to perform on-memory error correction that is to be disabled for platform error correction.

Abstract: A technique includes determining that a row of memory has been activated at a threshold rate. Upon reaching the threshold rate, a refresh rate for the row of memory and an adjacent row of memory may be increased. Subsequent to the increase, the refresh rate may be returned to a default rate.

Abstract: Example implementations relate to using a spare memory on a memory module. In example implementations, a memory module may have a plurality of memories, including default memories and a spare memory. A plurality of data buffers on the memory module may select data nibbles from the plurality of memories such that when a default memory is identified as defective, a data nibble is selected from the spare memory and not from the defective default memory. A data nibble selected from the default memory may be in a first position in an output of the memory module when the default memory is functional. A data nibble selected from the spare memory may be in a second position in the output of the memory module.

Abstract: A table may include first and second row addresses that are adjacent an activated row address. A first counter of the first row address may be incremented if the activated row address is not included in the table. A second counter of the second row address may also be incremented if the activated row address is not included in the table. The first row address may be refreshed if the first counter exceeds a counter threshold. The second row address may be refreshed if the second counter exceeds the counter threshold.

Abstract: Data and a first error detection code related to the data is received. That the received data is written correctly to a memory is validated based on the first error detection code and/or a comparison of the written data to the received data. An alert is generated if it is determined that the written data is incorrect.

Abstract: A controller may include circuitry to execute a management policy associated with a computer accessible resource based on a process identifier. The process identifier may be associated with a thread initiated by a set of instructions executed by a processor resource. The controller may be operatively coupled to a register to contain a process identifier.

Abstract: A technique includes receiving, by a device a command, wherein a response to the command is expected from the device within a predetermined response time. The device may selectively generate an error signal to allow time for the device to complete processing the command.

Abstract: A technique includes accessing error information generated in response to memory errors of a memory device. The error information generated in response to the memory errors of the memory device may then be determined as indicative of a row hammer error for the memory device.

Abstract: An example device in accordance with an aspect of the present disclosure includes a first error corrector to perform platform error correction based on a stride length. A memory includes a second error corrector that is to perform on-memory error correction that is to be disabled for platform error correction.

Abstract: A technique includes determining, via an analog circuit, where an access rate of a memory row associated with a memory device exceeds a threshold. In various examples, upon a determination that the access rate exceeds the threshold, the technique may further comprise generating an alert to indicate possible corruption of data stored in an adjacent row to the memory row.