Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Abstract: A method of forming high-k metal gates (HKMGs) includes removing a dummy gate structure formed over a first fin and a second fin to form a trench that exposes portions of the first fin and the second fin, forming a high-k dielectric layer over the exposed portions of the first fin and the second fin, forming a capping layer over the high-k dielectric layer, forming a hard mask layer over the capping layer, such that the hard mask layer fills the trench completely, forming an isolation feature in the hard mask layer between the first fin and the second fin, the isolation feature having sidewalls that extend through the capping layer, removing the hard mask layer to expose the capping layer and the sidewalls of the isolation feature, and forming a conductive electrode over the capping layer and along the sidewalls of the isolation feature.

Abstract: A coffee bean roasting-degree distribution measuring device includes a housing, a micro-processing unit, an image-capturing unit, a light-emitting unit, and a displaying unit. The housing has a first end and a second end opposite the first end with an accommodating space existing between the first end and the second end. The second end is disposed to surround a group of coffee beans under measurement. The micro-processing unit and the image-capturing unit are disposed inside the accommodating space and electrically connected to each other. The light-emitting unit is disposed inside the accommodating space and includes at least one light emitter and a circuit board electrically connected to the light emitter. The circuit board is further electrically connected to the micro-processing unit and each of the light emitter has a light emitting port facing toward the second end.

Abstract: An optical module includes a housing, and a main circuit board, an optical transmitting assembly, an optical receiving assembly, and an electrical connector that are disposed inside the housing. Each one of the optical transmitting assembly and optical receiving assembly includes at least two sets of optoelectronic chips, an optical assembly, and an optical fiber receptacle. The electrical connector electrically connects the optical transmitting assembly and/or optical receiving assembly to the main circuit board.

Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Abstract: The present disclosure relates to a wearable water triboelectric generator, wherein the water triboelectric generator comprises a first substrate having a first surface and a second surface, wherein the first surface and the second surface are opposing to each other; and wherein the first surface comprises a modified hydrophobic surface comprising a coating of hydrophobic cellulose oleoyl ester nanoparticles. There is also provided a wearable dual mode water and contact triboelectric generator comprising said water triboelectric generator and a contact triboelectric generator, wherein the water triboelectric generator and the contact triboelectric generator are arranged such that the first substrate of the water triboelectric generator completely surrounds or encapsulates the contact triboelectric generator.

Abstract: An inverter integrated motor having a frame (100), a motor body (200), a cap (300), a fan (400), an inverter (500), and a heat transfer module (600) is provided. The motor body (200) is received in the frame (100), and a heat dissipation passage (201a/201b) is formed between them, the motor body (200) is covered and closed by the cap (300), and the cap (300) and the motor body (200) are presented in a continuous form. The inverter (500) is attached on an outer side surface of the frame (100). The heat transfer module (600) is located between the cap (300) and the fan (400) and thermally connected to the inverter (500). Airflow is generated by the fan (400) to flow through the heat transfer module (600) and exchange heat therewith, and the airflow then flows into the heat dissipation passage (201a/201b) along the cap (300). Accordingly, an attached additional fan (400) for the inverter (500) is not necessary.

Abstract: A method of forming high-k metal gates (HKMGs) includes removing a dummy gate structure formed over a first fin and a second fin to form a trench that exposes portions of the first fin and the second fin, forming a high-k dielectric layer over the exposed portions of the first fin and the second fin, forming a capping layer over the high-k dielectric layer, forming a hard mask layer over the capping layer, such that the hard mask layer fills the trench completely, forming an isolation feature in the hard mask layer between the first fin and the second fin, the isolation feature having sidewalls that extend through the capping layer, removing the hard mask layer to expose the capping layer and the sidewalls of the isolation feature, and forming a conductive electrode over the capping layer and along the sidewalls of the isolation feature.

Abstract: An optical module includes a housing, and a main circuit board, an optical transmitting assembly, an optical receiving assembly, and an electrical connector that are disposed inside the housing. The optical transmitting assembly includes at least two sets of lasers, a transmitting-end optical assembly, and a transmitting-end optical fiber receptacle. The optical receiving assembly includes at least two sets of photoelectric detectors, a receiving-end optical assembly, and a receiving-end optical fiber receptacle. The electrical connector electrically connects the optical transmitting assembly and the optical receiving assembly to the main circuit board.

Abstract: An optical module includes a housing, and a main circuit board, an optical transmitting assembly, an optical receiving assembly, and an electrical connector that are disposed inside the housing. Each one of the optical transmitting assembly and optical receiving assembly includes at least two sets of optoelectronic chips, an optical assembly, and an optical fiber receptacle. The electrical connector electrically connects the optical transmitting assembly and/or optical receiving assembly to the main circuit board.

Abstract: A method of forming high-k metal gates (HKMGs) includes removing a dummy gate structure formed over a first fin and a second fin to form a trench that exposes portions of the first fin and the second fin, forming a high-k dielectric layer over the exposed portions of the first fin and the second fin, forming a capping layer over the high-k dielectric layer, forming a hard mask layer over the capping layer, such that the hard mask layer fills the trench completely, forming an isolation feature in the hard mask layer between the first fin and the second fin, the isolation feature having sidewalls that extend through the capping layer, removing the hard mask layer to expose the capping layer and the sidewalls of the isolation feature, and forming a conductive electrode over the capping layer and along the sidewalls of the isolation feature.

Abstract: A floating solar panel erection structure includes a floating platform, an angle adjustment mechanism and an angle restriction mechanism. The floating platform includes a chute, a first anchoring mechanism and a second anchoring mechanism. The angle adjustment mechanism includes a first link, a second link and a third link that are pivotally connected to the floating platform. The first link and the third link have first ends pivotally connected to the floating platform, the second link have two opposite ends pivotally connected to second opposite ends of the first link and the third link, and the second link is for erecting a solar panel thereon. The angle restriction mechanism has a latch link to be coupled to the third link, and an end of the latch link is connected with a sliding projection which is slidably connected within the chute.

Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Abstract: A semiconductor structure includes a substrate, at least two gate spacers, a gate stack, an insulating structure, and at least one sacrificial layer. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. The gate stack is disposed between the gate spacers and covers the semiconductor fin. The insulating structure is disposed between the gate spacers and adjacent to the gate stack. The sacrificial layer is disposed between at least one of the gate spacers and the insulating structure.

Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract: A laser driver for a laser, which includes an adjustable DC-DC power source, an optical power control loop, and a power source voltage regulator. The adjustable DC-DC power source is coupled to the optical power control loop and the power source voltage regulator, in order to provide a working current for the laser. The optical power control loop is configured to adjust the output optical power of the laser to a set value for optical power by adjusting a working voltage of the laser, and to generate a power source voltage state indicator voltage. The power source voltage regulator is used to generate the power source setting voltage, so that the power source voltage state indicator voltage is greater than or equal to a first preset threshold, or less than or equal to a second preset threshold.

Abstract: Method for preparing a ceramic-polymer nanocomposite is provided. The method includes providing a polymer comprising radicals on a surface thereof; contacting the polymer with a functionalizing agent to form a functionalized polymer; and either (i) grafting a cross-linking agent onto the functionalized polymer to form a graft copolymer, and attaching ceramic nanostructures to the graft copolymer to form a ceramic-polymer nanocomposite, or (ii) grafting a cross-linking agent onto ceramic nanostructures to form modified ceramic nanostructures, and attaching the modified ceramic nanostructures to the functionalized polymer to form a ceramic-polymer nanocomposite. A ceramic-polymer nanocomposite and use of the ceramic-polymer nanocomposite are also provided.

Abstract: Methods for forming a graft copolymer of a poly(vinylidene fluoride)-based polymer and at least one type of electrically conductive polymer, wherein the electrically conductive polymer is grafted on the poly(vinylidene fluoride)-based polymer are provided. The methods comprise a) irradiating a poly(vinylidene fluoride)-based polymer with a stream of electrically charged particles; b) forming a solution comprising the irradiated poly(vinylidene fluoride)-based polymer, an electrically conductive monomer and an acid in a suitable solvent; and c) adding an oxidant to the solution to form the graft copolymer. Graft copolymers of a poly(vinylidene fluoride)-based polymer and at least one type of electrically conductive polymer, wherein the electrically conductive polymer is grafted on the poly(vinylidene fluoride)-based polymer, nanocomposite materials comprising the graft copolymer, and multilayer capacitors comprising the nanocomposite material are also provided.

Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die.