Abstract: A laser driver for a laser, which includes an adjustable DC-DC power source, an optical power control loop, and a power source voltage regulator. The adjustable DC-DC power source is coupled to the optical power control loop and the power source voltage regulator, in order to provide a working current for the laser. The optical power control loop is configured to adjust the output optical power of the laser to a set value for optical power by adjusting a working voltage of the laser, and to generate a power source voltage state indicator voltage. The power source voltage regulator is used to generate the power source setting voltage, so that the power source voltage state indicator voltage is greater than or equal to a first preset threshold, or less than or equal to a second preset threshold.

Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die.

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract: Method for preparing a ceramic-polymer nanocomposite is provided. The method includes providing a polymer comprising radicals on a surface thereof; contacting the polymer with a functionalizing agent to form a functionalized polymer; and either (i) grafting a cross-linking agent onto the functionalized polymer to form a graft copolymer, and attaching ceramic nanostructures to the graft copolymer to form a ceramic-polymer nanocomposite, or (ii) grafting a cross-linking agent onto ceramic nanostructures to form modified ceramic nanostructures, and attaching the modified ceramic nanostructures to the functionalized polymer to form a ceramic-polymer nanocomposite. A ceramic-polymer nanocomposite and use of the ceramic-polymer nanocomposite are also provided.

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract: A route planning method includes: displaying, by an output device, a map and an original route from a departure point to a destination through at least two intermediate points on the map, the intermediate points being selected from a plurality of points of interest that are pre-stored in a storage device; transmitting, by an input device, an input signal to the processor in response to a user selection of a priority one of the intermediate points; upon receipt of the input signal, planning, by a processor, a modified route passing sequentially through the departure point, the priority one of the intermediate points, the remaining one(s) of the intermediate points and the destination; and displaying, by the output device, the modified route on the map.

Abstract: The embodiments described provide methods and semiconductor device areas for etching an active area region on a semiconductor body and epitaxially depositing a semiconductor layer overlying the active region. The methods enable the mitigation or elimination of problems encountered in subsequent manufacturing associated with STI divots.

Abstract: Methods for forming a graft copolymer of a poly(vinylidene fluoride)-based polymer and at least one type of electrically conductive polymer, wherein the electrically conductive polymer is grafted on the poly(vinylidene fluoride)-based polymer are provided. The methods comprise a) irradiating a poly(vinylidene fluoride)-based polymer with a stream of electrically charged particles; b) forming a solution comprising the irradiated poly(vinylidene fluoride)-based polymer, an electrically conductive monomer and an acid in a suitable solvent; and c) adding an oxidant to the solution to form the graft copolymer. Graft copolymers of a poly(vinylidene fluoride)-based polymer and at least one type of electrically conductive polymer, wherein the electrically conductive polymer is grafted on the poly(vinylidene fluoride)-based polymer, nanocomposite materials comprising the graft copolymer, and multilayer capacitors comprising the nanocomposite material are also provided.

Abstract: The embodiments described provide methods and semiconductor device areas for etching an active area region on a semiconductor body and epitaxially depositing a semiconductor layer overlying the active region. The methods enable the mitigation or elimination of problems encountered in subsequent manufacturing associated with STI divots.

Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die.

Abstract: A USB port transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one USB transmission from among multiple scheduled USB transmissions based on their types. A selector selects one of the arbiters to select the one USB transmission from among the multiple scheduled USB transmissions. A programmable storage element controls the selector to select the one arbiter. In one embodiment, at least a first arbiter prioritizes header/data packets higher than link commands, and at least a second arbiter prioritizes link commands higher than header/data packets. In one embodiment, at least one arbiter prioritizes flow control and power management link commands higher than header/data packets. In one embodiment, at least a first of the arbiters prioritizes USB LGO_Ux link commands higher than USB LAU/LXU link commands, and at least a second arbiter prioritizes USB LAU/LXU link commands higher than USB LGO_Ux link commands.

Abstract: A USB port transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one USB transmission from among multiple scheduled USB transmissions based on their types. A selector selects one of the arbiters to select the one USB transmission from among the multiple scheduled USB transmissions. A programmable storage element controls the selector to select the one arbiter. In one embodiment, at least a first arbiter prioritizes header/data packets higher than link commands, and at least a second arbiter prioritizes link commands higher than header/data packets. In one embodiment, at least one arbiter prioritizes flow control and power management link commands higher than header/data packets. In one embodiment, at least a first of the arbiters prioritizes USB LGO_Ux link commands higher than USB LAU/LXU link commands, and at least a second arbiter prioritizes USB LAU/LXU link commands higher than USB LGO_Ux link commands.

Abstract: An improved overmolded electronic assembly includes a backplate provided with a recessed edge, a circuit substrate on the backplate, at least one electronic component mounted on the circuit substrate, conductive traces on the circuit substrate which together with the electronic component(s) defines a circuit device, an electrical connector, and an overmold body that has peripheral edges that wrap around sides of the backplate and onto the edge recesses. The resulting over wrap feature eliminates delamination problems that would otherwise occur during thermal cycling of the electronic assembly, improves corrosion resistance at connector-to-backplate interfaces, and enhances securement of the printed circuit board assembly and electrical connector to the assembly.

Abstract: An improved overmolded electronic assembly includes a backplate, a circuit substrate on the backplate, at least one electronic component mounted on the circuit substrate, conductive traces on the circuit substrate which together with the electronic component(s) defines a circuit device, an electrical connector having a thermoplastic body and electrical conducting elements embedded in and extending through the thermoplastic body to define internal and external connectors, and an overmold body that is mechanically interlocked with protuberances integrally formed on the thermoplastic body of the electrical connector.

Abstract: An improved overmolded electronic assembly includes a backplate provided with a recessed edge, a circuit substrate on the backplate, at least one electronic component mounted on the circuit substrate, conductive traces on the circuit substrate which together with the electronic component(s) defines a circuit device, an electrical connector, and an overmold body that has peripheral edges that wrap around sides of the backplate and onto the edge recesses. The resulting over wrap feature eliminates delamination problems that would otherwise occur during thermal cycling of the electronic assembly, improves corrosion resistance at connector-to-backplate interfaces, and enhances securement of the printed circuit board assembly and electrical connector to the assembly.

Abstract: A partially overmolded component having a precisely defined overmolding edge includes a component having a protruding elongate rib and the overmolding having a terminal edge abutting the protruding elongate rib. The rib defines surfaces that provide a greater area of contact between the component and an overmolding tool and a more tortuous flow path to bleed-through.

Abstract: An improved overmolded electronic assembly includes a backplate, a circuit substrate on the backplate, at least one electronic component mounted on the circuit substrate, conductive traces on the circuit substrate which together with the electronic component(s) defines a circuit device, an electrical connector, a metal ring on an outer side of a thermoplastic wall member of the electrical connector, and an overmold body. The metal ring circumscribes external connector pins of the electrical connector, and the overmold body together with the backplate and thermoplastic wall member of the electrical connector sealingly encase the circuit substrate and the circuit device defined on the substrate, with the overmold body having a peripheral edge in adhesive contact with the metal ring. The invention avoids delamination problems associate with similar arrangements which do not incorporate a metal ring.

Abstract: A partially overmolded component having a precisely defined overmolding edge includes a component having a protruding elongate rib and the overmolding having a terminal edge abutting the protruding elongate rib. The rib defines surfaces that provide a greater area of contact between the component and an overmolding tool and a more tortuous flow path to bleed-through.

Abstract: A mold has at least one vent hole formed in the mold. The vent hole is positioned to allow egress of air from the mold. The vent hole has an inside end and an outside end. The vent hole has a cross section that increases in area from the inside end to the outside end. The vent hole may have a shape of a trapezoidal prism, a truncated pyramid or a truncated cone; the cross section of the vent hole may be a rectangle. A preferred mold has three air vent holes at three corners of the mold. An integrated circuit is placed within the mold. A material to be molded is injected into the mold to encapsulate the integrated circuit. Mold cleaning is facilitated by the shape of the vent, and plastic flashes may be easily removed through the vent hole.