Patents by Inventor Meng-Hung Shen
Meng-Hung Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230275096Abstract: In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess.Type: ApplicationFiled: May 8, 2023Publication date: August 31, 2023Inventors: Te-Hsin Chiu, Shih-Wei Peng, Meng-Hung Shen, Jiann-Tyng Tzeng
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Publication number: 20230259685Abstract: A layout method includes: providing a library comprising a first cell and a second cell, wherein each of the first and second cells includes: a first active region and a second active region extending in a first direction; a first cell-edge gate structure and a second cell-edge gate structure extending in a second direction; and a third cell-edge gate structure and a fourth cell-edge gate structure extending in the second direction, wherein each of the first and second cell further includes one of a tie-off conductive line or a tie-off marker layer on each of the first and second cell-edge gate structures. The layout method further includes: generating a design layout by placing and abutting the first cell and the second cell; updating the design layout by performing a post-processing step on the tie-off conductive line and the tie-off marker layer of each of the first and second cells.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Inventors: JIANN-TYNG TZENG, SHIH-WEI PENG, MENG-HUNG SHEN, WEI-AN LAI
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Publication number: 20230154846Abstract: A method of making a semiconductor structure includes defining a first recess in an insulation layer. The method further includes forming a protection layer along a sidewall of the first recess. The method further includes forming a first conductive line in the first recess and in direct contact with the protection layer. The method further includes depositing a first insulation material over the first conductive line. The method further includes defining a second recess in the first insulation material. The method further includes forming a second conductive line in the second recess. The method further includes forming a via extending from the second conductive line, wherein the via directly contacts a sidewall of the protection layer.Type: ApplicationFiled: January 19, 2023Publication date: May 18, 2023Inventors: Te-Hsin CHIU, Wei-An LAI, Meng-Hung SHEN, Wei-Cheng LIN, Jiann-Tyng TZENG, Kam-Tou SIO
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Patent number: 11646314Abstract: In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess. In some embodiments, the method further includes partially exposing the semiconductor region in a second recess in the first dielectric material and selectively depositing the second dielectric material on the first dielectric material, but not the semiconductor region, in the second recess.Type: GrantFiled: April 16, 2021Date of Patent: May 9, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Hsin Chiu, Shih-Wei Peng, Meng-Hung Shen, Jiann-Tyng Tzeng
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Publication number: 20230113294Abstract: A method includes: disposing a first conductive segment; disposing a first conductive via above the first conductive segment; disposing a first conductive line above the first conductive via; and disposing a second conductive segment electrically coupled to the first conductive line through a third conductive segment, the first conductive segment, and the first conductive via.Type: ApplicationFiled: December 12, 2022Publication date: April 13, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Hung SHEN, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kam-Tou SIO, Wei-Cheng LIN
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Publication number: 20230103578Abstract: A semiconductor structure includes a first conductive line, a first conductive segment, a second conductive segment, and a third conductive segment. The first conductive segment is electrically coupled to the first conductive line. The second conductive segment is electrically coupled the first conductive segment. The second conductive segment is disposed between the first conductive segment and the third conductive segment. A top surface of the first conductive segment is aligned with a top surface of the second conductive segment in a same layer.Type: ApplicationFiled: December 12, 2022Publication date: April 6, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Hung SHEN, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kam-Tou SIO, Wei-Cheng LIN
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Publication number: 20230048735Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.Type: ApplicationFiled: October 28, 2022Publication date: February 16, 2023Inventors: Po-Chia LAI, Meng-Hung Shen, Chi-Lin Liu, Stefan Rusu, Yan-Hao Chen, Jerry Chang-Jui Kao
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Patent number: 11574110Abstract: A method of fabricating an integrated circuit structure includes placing a first set of conductive structure layout patterns on a first layout level, placing a second set of conductive structure layout patterns on a second layout level, placing a first set of via layout patterns between the second set of conductive structure layout patterns and the first set of conductive structure layout patterns, and manufacturing the integrated circuit structure based on at least one of the layout patterns of the integrated circuit. At least one of the layout patterns is stored on a non-transitory computer-readable medium, and at least one of the placing operations is performed by a hardware processor. The first set of conductive structure layout patterns extends in a first direction. The second set of conductive structure layout patterns extends in the second direction, and overlap the first set of conductive structure layout patterns.Type: GrantFiled: November 30, 2018Date of Patent: February 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
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Patent number: 11569166Abstract: The present disclosure provides a semiconductor structure, including a substrate, a first metal line over the substrate and extending along a first direction, a protection layer lining a sidewall of the first metal line, a second metal line above the first metal line and extending along the first direction, and a third metal line above the second metal line, extending along a second direction perpendicular to the first direction.Type: GrantFiled: December 16, 2020Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Hsin Chiu, Wei-An Lai, Meng-Hung Shen, Wei-Cheng Lin, Jiann-Tyng Tzeng, Kam-Tou Sio
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Patent number: 11532553Abstract: A semiconductor structure is disclosed that includes a first conductive line, a first conductive segment, a second conductive segment, and a gate. The first conductive segment is electrically coupled to the first conductive line through a conductive via. The second conductive segment is configured to electrically couple the first conductive segment with a third conductive segment disposed over an active area. The gate is disposed under the second conductive segment and disposed between first conductive segment and the third conductive segment. The first conductive line and the second conductive segment are disposed at two sides of the conductive via respectively. A length of the first conductive segment is greater than a length of the third conductive segment.Type: GrantFiled: December 23, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Hung Shen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin
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Publication number: 20220382951Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Jung-Chan YANG, Ting-Wei CHIANG, Jerry Chang-Jui KAO, Hui-Zhong ZHUANG, Lee-Chung LU, Li-Chun TIEN, Meng-Hung SHEN, Shang-Chih HSIEH, Chi-Yu LU
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Publication number: 20220336458Abstract: In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess.Type: ApplicationFiled: April 16, 2021Publication date: October 20, 2022Inventors: Te-Hsin Chiu, Shih-Wei Peng, Meng-Hung Shen, JIann-Tyng Tzeng
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Publication number: 20220328397Abstract: A method for fabricating a semiconductor structure includes depositing a first insulation material over a substrate, wherein the substrate includes an active region. The method further includes etching the first insulation material to define a first recess extending along a first direction at a first level of the first insulation material. The method further includes depositing a second insulation material lining with a sidewall of the first recess. The method further includes depositing a first metal line in the first recess.Type: ApplicationFiled: June 22, 2022Publication date: October 13, 2022Inventors: Te-Hsin CHIU, Wei-An LAI, Meng-Hung SHEN, Wei-Cheng LIN, Jiann-Tyng TZENG, Kam-Tou SIO
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Patent number: 11461528Abstract: An integrated circuit structure includes a first, a second and a third set of conductive structures and a first and a second set of vias. The first set of conductive structures extend in a first direction, and is located at a first level. The second set of conductive structures extends in a second direction, overlaps the first set of conductive structures, and is located at a second level. The first set of vias is between, and electrically couples the first and the second set of conductive structures. The third set of conductive structures extends in the first direction, overlaps the second set of conductive structures, covers a portion of the first set of conductive structures, and is located at a third level. The second set of vias is between, and electrically couples the second and the third set of conductive structures.Type: GrantFiled: June 22, 2020Date of Patent: October 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
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Publication number: 20220238515Abstract: An integrated circuit is provided, including a first conductive pattern, at least one first conductive segment, and a first via. The first conductive pattern is disposed in a first layer and configured as a terminal of an inverter. The at least one first conductive segment is disposed in a second layer above the first layer and configured to transmit an output signal output from the inverter. The first via contacts the first conductive pattern and the at least one first conductive segment to transmit the output signal. An area, contacting the first conductive pattern, of the first via is smaller than an area, contacting the at least one first conductive segment, of the first via.Type: ApplicationFiled: April 13, 2022Publication date: July 28, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Chia LAI, Shang-Wei FANG, Meng-Hung SHEN, Jiann-Tyng TZENG, Ting-Wei CHIANG, Jung-Chan YANG, Stefan RUSU
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Patent number: 11309311Abstract: An integrated circuit is disclosed, including a first conductive pattern and a second conductive pattern that are disposed in a first layer and extend in a first direction, at least one first conductive segment disposed in a second layer different from the first layer, and at least one via disposed between the first layer and the second layer. The at least one via is coupled between the at least one first conductive segment and one or both of the first conductive pattern and the second conductive pattern, at an output node of the integrated circuit. The at least one via comprises a tapered shape with a width that decreases from a first width to a second width narrower than the first width. The first width of the at least one via is greater than widths of the first conductive pattern and the second conductive pattern.Type: GrantFiled: February 11, 2020Date of Patent: April 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Chia Lai, Shang-Wei Fang, Meng-Hung Shen, Jiann-Tyng Tzeng, Ting-Wei Chiang, Jung-Chan Yang, Stefan Rusu
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Publication number: 20220068791Abstract: The present disclosure provides a semiconductor structure, including a substrate, a first metal line over the substrate and extending along a first direction, a protection layer lining a sidewall of the first metal line, a second metal line above the first metal line and extending along the first direction, and a third metal line above the second metal line, extending along a second direction perpendicular to the first direction.Type: ApplicationFiled: December 16, 2020Publication date: March 3, 2022Inventors: Te-Hsin CHIU, Wei-An LAI, Meng-Hung SHEN, Wei-Cheng LIN, Jiann-Tyng TZENG, Kam-Tou SIO
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Publication number: 20210249407Abstract: An integrated circuit is disclosed, including a first conductive pattern and a second conductive pattern that are disposed in a first layer and extend in a first direction, at least one first conductive segment disposed in a second layer different from the first layer, and at least one via disposed between the first layer and the second layer. The at least one via is coupled between the at least one first conductive segment and one or both of the first conductive pattern and the second conductive pattern, at an output node of the integrated circuit. The at least one via comprises a tapered shape with a width that decreases from a first width to a second width narrower than the first width. The first width of the at least one via is greater than widths of the first conductive pattern and the second conductive pattern.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Inventors: Po-Chia LAI, Shang-Wei FANG, Meng-Hung SHEN, Jiann-Tyng TZENG, Ting-Wei CHIANG, Jung-Chan YANG, Stefan RUSU
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Patent number: 11043426Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.Type: GrantFiled: September 22, 2019Date of Patent: June 22, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hui-Ting Yang, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Meng-Hung Shen, Ru-Gun Liu, Wei-Cheng Lin
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Publication number: 20210175876Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.Type: ApplicationFiled: February 19, 2021Publication date: June 10, 2021Inventors: Po-Chia LAI, Meng-Hung SHEN, Chi-Lin LIU, Stefan RUSU, Yan-Hao CHEN, Jerry Chang-Jui KAO