Patents by Inventor Meng Jung

Meng Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240150532
    Abstract: A prepreg and uses thereof are provided. The prepreg includes an organic fiber woven fabric impregnated or coated with a thermally curable resin composition, wherein the thermally curable resin composition includes: (A) a polyphenylene ether resin having an unsaturated functional group; (B) a polyfunctional vinyl aromatic copolymer; and (C) a compound having the structure of formula (I), wherein, in formula (I), X is a C1-C10 linear or branched alkylene; and the polyfunctional vinyl aromatic copolymer is prepared by copolymerizing one or more divinyl aromatic compounds with one or more monovinyl aromatic compounds.
    Type: Application
    Filed: November 10, 2022
    Publication date: May 9, 2024
    Inventors: Wei-Jung YANG, Meng-Huei CHEN
  • Publication number: 20240145302
    Abstract: A semiconductor device and a method for manufacturing an interconnecting metal layer thereof are provided. The semiconductor device includes a gate layer, a dielectric layer, an insulating layer, an epitaxial layer, and a sidewall liner. The dielectric layer is disposed on one side of the gate layer, the insulating layer is disposed on another side of the gate layer, the epitaxial layer is located on the insulating layer, and the sidewall liner penetrates the dielectric layer and the gate layer, and one end of the sidewall liner is connected to the epitaxial layer. The sidewall liner is converted from a high-k material to a low-k material by hydrogen and oxygen plasma treatments.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Shien SHIAH, Bor Chiuan HSIEH, Tsai-Jung HO, Meng-Ku CHEN, Tze-Liang LEE
  • Publication number: 20240140970
    Abstract: Described is a deuterated compound, and preparation method and use thereof The deuterated compound I has a structure as shown in Formula (I), wherein A is H or D, and at least one of eight As is D; M is H or an alkali metal, an alkaline earth metal, or an ammonium radical. The present invention provides use of the deuterated compound I as an internal standard for measuring the content of a metabolite II in a biological sample, wherein the metabolite II has a structure as shown in a Formula (II); wherein A is H; M is H or an alkali metal, an alkaline earth metal, or an ammonium radical. The present invention uses the deuterated compound I as an internal standard to quantitatively analysis the content of metabolite II at lower content in biological samples, which can not only meet the requirements for the lower limit of quantitation, but also meet the requirements for DMPK studies in clinical trials.
    Type: Application
    Filed: November 26, 2021
    Publication date: May 2, 2024
    Inventors: Meizhen Ruan, Xiaohong Cai, Jianxin Duan, Donald T Jung, Anrong Li, Teng Meng, Lin Sun, Bing Li
  • Patent number: 11973027
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Yu Chou, Jr-Hung Li, Liang-Yin Chen, Su-Hao Liu, Tze-Liang Lee, Meng-Han Chou, Kuo-Ju Chen, Huicheng Chang, Tsai-Jung Ho, Tzu-Yang Ho
  • Patent number: 11967291
    Abstract: A display may have a pixel array such as a liquid crystal pixel array. The pixel array may be illuminated by a backlight unit that includes an array of light-emitting diodes (LEDs). The backlight unit may determine the type of content in the image data. The backlight unit may decide to prioritize either mitigating halo or mitigating clipping based on the type of content. The determination of the type of content in the image data may be used to determine the brightness values for the LEDs in the LED array. If the content is determined to be a first type of content, at least one given LED in the LED array may have a different brightness value than if the content is determined to be a second, different type of content. Classifying content in the image data may be useful in optimizing visible artifacts such as visible halo and clipping.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: April 23, 2024
    Assignee: Apple Inc.
    Inventors: Mohammad Tofighi, Meng Cao, Pierre-Yves Emelie, Duane M Petrovich, Shuo Han, Zhendong Hong, Tobias Jung, Marc Albrecht, Jiulong Shan, Wei H Yao
  • Patent number: 11959956
    Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 16, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 11953738
    Abstract: The present invention discloses a display including a display panel and a light redirecting film disposed on the viewing side of the display panel. The light redirecting film comprises a light redistribution layer, and a light guide layer disposed on the light redistribution layer. The light redistribution layer includes a plurality of strip-shaped micro prisms extending along a first direction and arranged at intervals and a plurality of diffraction gratings arranged at the bottom of the intervals between the adjacent strip-shaped micro prisms, wherein each of the strip-shaped micro prisms has at least one inclined light-guide surface, and the bottom of each interval has at least one set of diffraction gratings, and the light guide layer is in contact with the strip-shaped micro prisms and the diffraction gratings.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: April 9, 2024
    Assignee: BenQ Materials Corporation
    Inventors: Cyun-Tai Hong, Yu-Da Chen, Hsu-Cheng Cheng, Meng-Chieh Wu, Chuen-Nan Shen, Kuo-Jung Huang, Wei-Jyun Chen, Yu-Jyuan Dai
  • Publication number: 20240097888
    Abstract: In a file sharing system, a key manager unit realizes a correspondence between the first user identifier and the first public key in response to a registration request of the first user, generates a first key material for encrypting the first file into a first encrypted file, and generates a first credential according to the first user identifier, the first file identifier, the first public key and the first key material after receiving an access-right claim request to the first file from the first user. A file storage unit stores the first encrypted file and the first credential. The first user uses the first user identifier, the first file identifier and the first private key to retrieve the first key material out of the first credential, and uses the first key material to decrypt the first encrypted file into the first file.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 21, 2024
    Inventors: CHIA-JUNG LIANG, CHIHHUNG LIN, CHIH-PING HSIAO, YU-JIE SU, CHIA-HSIN CHENG, TUN-HOU WANG, MENG-CHAO TSAI, YUEH-CHIN LIN
  • Patent number: 11804410
    Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: October 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-De Ho, Han-Wei Wu, Pei-Sheng Tang, Meng-Jung Lee, Hua-Tai Lin, Szu-Ping Tung, Lan-Hsin Chiang
  • Publication number: 20230087546
    Abstract: An energy storage system is provided for an electric vehicle. The energy storage system comprises a first energy storage source. The first energy storage source includes an ammonia tank configured to hold ammonia, an ammonia converter configured to receive ammonia from the ammonia tank and convert the received ammonia into hydrogen, and a fuel cell system communicating with the ammonia converter and configured to generate output power from hydrogen that is received from the ammonia converter.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 23, 2023
    Inventors: Ka Wai Eric CHENG, Molly Meng-Jung LI, Shu Ping LAU, Shuangxia NIU
  • Publication number: 20230075145
    Abstract: A processing system is adapted to execute a method for testing power leakage of a circuit. The method includes: obtaining a plurality of undefined nets according to a netlist and power mode information; obtaining a trace path according to the undefined nets and the power mode information; and determining whether there is a risk of power leakage in the trace path, and outputting a testing result.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 9, 2023
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Meng-Jung Lee, Yu-Lan Lo
  • Publication number: 20230043018
    Abstract: A smart ring includes a battery, memory, processing circuitry, a plurality of sensors, a plurality of antennas, and a battery, each coupled to one another and all enclosed in a casing, wherein the processing circuitry is configured to conserve the battery by any of sending data to the cloud service when an application is open on the user device, sending data to the cloud service when a threshold is crossed, waking up processing or communicating when there is a change in motion detected by the accelerometer.
    Type: Application
    Filed: April 6, 2022
    Publication date: February 9, 2023
    Inventors: Crystal Wai, Shuhan Liu, Hsiangyin Cheng, Meng-Jung Chuang, Liem Hieu Dinh Vo, Richard Chang, Ming-Tsung Su, Hao-Hsiu Huang, Jeffrey ChiFai Liew, Zhicheng Qiu, Cuong Vu, Fahri Diner, Miroslav Samardzija, Shu Chun Shen
  • Publication number: 20220359313
    Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Wei-De HO, Han-Wei WU, Pei-Sheng TANG, Meng-Jung LEE, Hua-Tai LIN, Szu-Ping TUNG, Lan-Hsin CHIANG
  • Publication number: 20220238502
    Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.
    Type: Application
    Filed: April 12, 2022
    Publication date: July 28, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yueh TSAI, Meng-Jen WANG, Yu-Fang TSAI, Meng-Jung CHUANG
  • Patent number: 11302682
    Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 12, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tsung-Yueh Tsai, Meng-Jen Wang, Yu-Fang Tsai, Meng-Jung Chuang
  • Publication number: 20210190844
    Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 24, 2021
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 11010521
    Abstract: A method of detecting the relations between the pins of a circuit and a computer program product thereof are provided. The method includes: retrieving a circuit description file describing a circuit; retrieving at least one data pin and at least one clock pin of the circuit; converting the circuit to a cell level; and tracing the circuit in the cell level to identify multiple flip-flops coupled to the clock pin; tracing the circuit in the cell level to identify a target flip-flop coupled to the data pin; and determining whether the data pin is related to the clock pin according to the data signal and the clock signal of the target flip-flop.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: May 18, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chia-Ling Hsu, Ting-Hsiung Wang, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao
  • Publication number: 20210125974
    Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 29, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yueh TSAI, Meng-Jen WANG, Yu-Fang TSAI, Meng-Jung CHUANG
  • Publication number: 20210066139
    Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.
    Type: Application
    Filed: March 5, 2020
    Publication date: March 4, 2021
    Inventors: Wei-De HO, Han-Wei WU, Pei-Sheng TANG, Meng-Jung LEE, Hua-Tai LIN, Szu-Ping TUNG, Lan-Hsin CHIANG
  • Publication number: 20210012050
    Abstract: A method of detecting the relations between the pins of a circuit and a computer program product thereof are provided. The method includes: retrieving a circuit description file describing a circuit; retrieving at least one data pin and at least one clock pin of the circuit; converting the circuit to a cell level; and tracing the circuit in the cell level to identify multiple flip-flops coupled to the clock pin; tracing the circuit in the cell level to identify a target flip-flop coupled to the data pin; and determining whether the data pin is related to the clock pin according to the data signal and the clock signal of the target flip-flop.
    Type: Application
    Filed: July 6, 2020
    Publication date: January 14, 2021
    Inventors: CHIA-LING HSU, TING-HSIUNG WANG, MENG-JUNG LEE, YU-LAN LO, SHU-YI KAO