Abstract: A method for forming a package structure is provided. The method includes forming first conductive structures and a first semiconductor die on a same side of a redistribution structure. The method includes forming an interposer substrate over the redistribution structure, wherein the first semiconductor die is between the interposer substrate and the redistribution structure, and edges of the interposer substrate extend beyond edges of the first semiconductor die. The method includes forming a second semiconductor die on the redistribution structure, wherein the first semiconductor die and the second semiconductor die are disposed on opposite sides of the redistribution structure.

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Abstract: The present disclosure is directed to methods and devices for devices including multiple die. A wafer is received having a plurality of die and a plurality of scribe lines. A dicing process is performed on the wafer. The dicing process includes identifying a first scribe line of the plurality of scribe lines, the first scribe line interposing a first die and a second die of the plurality of die; and performing a partial cut on the first scribe line. In embodiments, other scribe lines of the wafer are, during the dicing process, fully cut. After the dicing, the first die and the second die are mounted on a substrate such as an interposer. The first die and the second die are connected by a portion of the first scribe line, e.g., remaining from the partial cut, during the mounting.

Abstract: An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate, implanting n-type impurities into a device region in the semiconductor substrate to form an implanted region and an un-implanted region. The method also includes forming an epitaxial layer on the semiconductor substrate and forming a trench surrounding the device region in direct contact with the implanted region. The method further includes performing a selective lateral etch through the trench to remove the implanted region to form a cavity under the epitaxial layer. The un-implanted region is retained to form a pillar under the epitaxial layer. Next, an insulating material is disposed in the cavity and the trench. The method forms a single crystalline region that is separated from the semiconductor substrate by the insulating material except at the pillar.

Abstract: A semiconductor device includes: a die having die connectors at a front side of the die; a molding material around the die; and a redistribution structure, where the die connectors of the die are attached to a first side of the redistribution structure, where the redistribution structure includes: a dielectric layer; a conductive line extending along a first surface of the dielectric layer facing the die; and a warpage tuning layer contacting and extending along a first surface of the conductive line facing the die, where a first coefficient of thermal expansion (CTE) of the conductive line is smaller than a second CTE of the warpage tuning layer.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.

Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.

Abstract: A package structure is provided. The package structure includes an interposer substrate including an insulating structure, a conductive pad, a first conductive line, and a first conductive via structure. The package structure includes an electronic device bonded to the conductive pad. The package structure includes a chip structure bonded to the first end portion of the first conductive via structure. The package structure includes a first conductive bump connected between the chip structure and the first end portion of the first conductive via structure. The first end portion protrudes into the first conductive bump and is in direct contact with the first conductive bump.

Abstract: An embodiment semiconductor device includes an interposer, a semiconductor die electrically connected to the interposer, an integrated passive device die electrically connected to the interposer, the integrated passive device die including two or more seal rings, and a first alignment mark formed on the integrated passive device die within a first area enclosed by a first one of the two or more seal rings. The integrated passive device die may further include two or more integrated passive devices located within respective areas enclosed by respective ones of the two or more seal rings. Each of the two or more integrated passive devices may include electrical connections that are formed as a plurality of micro-bumps, and the first alignment mark may be electrically isolated from the electrical connections, and the first alignment mark and the electrical connections may share a common material.

Abstract: A semiconductor structure includes an interposer including redistribution wiring interconnects and redistribution insulating layers; a first semiconductor die attached to the interposer through a first array of solder material portions; and a second semiconductor die attached to the interposer through a second array of solder material portions. The interposer includes at least one inductor structure located between an area of the first array of solder material portions and an area of the second array of solder material portions in a plan view and laterally encloses a respective area in the plan view.

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.

Abstract: A semiconductor package includes an interconnect structure, a plurality of dies disposed on the interconnect structure in a side-by-side manner, an underfill filling between the interconnect structure and the plurality of dies and filling a lower part of a gap between adjacent two of the plurality of dies, a conductive layer at least covering back surfaces of the adjacent two of the plurality of dies and filling an upper part of the gap, and an encapsulating material laterally encapsulating the plurality of dies and the conductive layer.

Abstract: A package is provided in accordance with some embodiments. The package includes a substrate including a first conductive via embedded in a first substrate core; a conductive pattern disposed on the first substrate core, wherein the conductive pattern includes a first conductive pad and a second conductive pad; a second substrate core disposed on the first substrate core and the conductive pattern; and a second conductive via disposed in the second substrate core and on the second conductive pad. The package also includes an encapsulant embedded in the second substrate core and in physical contact with the first conductive pad; a first die, including die connectors, embedded in the encapsulant and disposed on the first conductive pad; a redistribution structure disposed on the second conductive via, the die connectors and the encapsulant; and a second die disposed on the redistribution structure.

Abstract: An interposer for a semiconductor package and a method of fabricating an interposer including a peripheral metal pad surrounding an alignment mark. The alignment mark and the surrounding peripheral metal pad are formed on a first dielectric material layer of the interposer. A second dielectric material layer is located over the first dielectric material layer and at least partially over the peripheral metal pad structure and includes an recess extending around a periphery of the alignment mark. A third dielectric material layer is located over the second dielectric material layer and extends into the recess and contacts the alignment mark, the first dielectric material layer, and optionally a portion of the peripheral metal pad. The peripheral metal pad may enhance the adhesion between the first, second and third dielectric material layers near the alignment mark structure and thereby reduce the likelihood of crack formation.

Abstract: Semiconductor packages and methods of fabricating semiconductor packages include bonding structures on a surface of an interposer having non-uniform height dimensions in different regions of the interposer. A plurality of solder connections may contact the pillars and electrically connect the respective pillars of the interposer to corresponding bonding structures on a package substrate. The variation in the heights of the pillars in different regions of the interposer may compensate for warping of the interposer and improve the reliability of the electrical connections between the interposer and the package substrate.

Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

Abstract: A semiconductor structure includes a packaging substrate containing at least one trench located between a first region and a second region, a first chip module bonded to the first region of the packaging substrate through first solder material portions, and a second chip module bonded to the second region of the packaging substrate through second solder material portions. A first underfill material portion laterally surrounds the first solder material portions and extends into a first portion of the at least one trench. A second underfill material portion laterally surrounds the second solder material portions and extends into a second portion of the at least one trench. The at least one trench is used to absorb stress to the underfill material portions.