Patents by Inventor Meng-Liang Lin

Meng-Liang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194556
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.
    Type: Application
    Filed: February 16, 2024
    Publication date: June 13, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Liang Lin, Po-Yao Chuang, Te-Chi Wong, Shuo-Mao Chen, Shin-Puu Jeng
  • Publication number: 20240186397
    Abstract: In accordance with some aspects of the disclosure, a semiconductor structure is provided. The semiconductor structure includes: an active region; and a gate stack disposed on the active region. The gate stack includes: at least one gate dielectric layer disposed on the active region; and a metal gate structure disposed on the at least one gate dielectric layer. The metal gate structure includes: a metal gate layer comprising a first material; and at least one dummy structure disposed in the metal gate layer, the at least one dummy structure extending vertically through an entire thickness of the metal gate structure and comprising a second material. The second material is different from the first material.
    Type: Application
    Filed: February 24, 2023
    Publication date: June 6, 2024
    Inventors: Yu-Chen Chang, Anhao Cheng, Meng-I Kang, Yen-Liang Lin
  • Publication number: 20240178116
    Abstract: A semiconductor package includes a redistribution structure and an encapsulated die electrically connected to the redistribution structure. The redistribution structure includes a first conductive pad, first and second conductive vias, and a first dielectric layer. The first conductive pad includes opposing first and second sides, the first conductive via lands on the first side of the first conductive pad and is tapered in a direction from the first side toward the second side. The second conductive via lands on the second side of the first conductive pad and is tapered in a direction from the second side toward the first side. The first dielectric layer laterally covers the first conductive pad and the first conductive via, and the first dielectric layer includes opposing first and second surfaces. The encapsulated die is disposed below the first side of the first conductive via.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Yi-Wen Wu, Po-Yao Chuang
  • Patent number: 11948892
    Abstract: A method for forming a package structure is provided. The method includes forming first conductive structures and a first semiconductor die on a same side of a redistribution structure. The method includes forming an interposer substrate over the redistribution structure, wherein the first semiconductor die is between the interposer substrate and the redistribution structure, and edges of the interposer substrate extend beyond edges of the first semiconductor die. The method includes forming a second semiconductor die on the redistribution structure, wherein the first semiconductor die and the second semiconductor die are disposed on opposite sides of the redistribution structure.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hao Tsai, Meng-Liang Lin, Po-Yao Chuang, Techi Wong, Shin-Puu Jeng
  • Publication number: 20240105705
    Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
  • Publication number: 20240087902
    Abstract: The present disclosure is directed to methods and devices for devices including multiple die. A wafer is received having a plurality of die and a plurality of scribe lines. A dicing process is performed on the wafer. The dicing process includes identifying a first scribe line of the plurality of scribe lines, the first scribe line interposing a first die and a second die of the plurality of die; and performing a partial cut on the first scribe line. In embodiments, other scribe lines of the wafer are, during the dicing process, fully cut. After the dicing, the first die and the second die are mounted on a substrate such as an interposer. The first die and the second die are connected by a portion of the first scribe line, e.g., remaining from the partial cut, during the mounting.
    Type: Application
    Filed: January 19, 2023
    Publication date: March 14, 2024
    Inventors: Chieh-Lung LAI, Meng-Liang LIN, Chun-Yueh YANG, Hsien-Wei CHEN
  • Publication number: 20240079356
    Abstract: An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 7, 2024
    Inventors: Hsien-Wei Chen, Chieh-Lung Lai, Meng-Liang Lin, Chun-Yueh Yang, Shin-Puu Jeng
  • Publication number: 20240071812
    Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate, implanting n-type impurities into a device region in the semiconductor substrate to form an implanted region and an un-implanted region. The method also includes forming an epitaxial layer on the semiconductor substrate and forming a trench surrounding the device region in direct contact with the implanted region. The method further includes performing a selective lateral etch through the trench to remove the implanted region to form a cavity under the epitaxial layer. The un-implanted region is retained to form a pillar under the epitaxial layer. Next, an insulating material is disposed in the cavity and the trench. The method forms a single crystalline region that is separated from the semiconductor substrate by the insulating material except at the pillar.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Chung-Lei Chen, Anhao Cheng, Meng-I Kang, Yen-Liang Lin
  • Publication number: 20240063083
    Abstract: A semiconductor device includes: a die having die connectors at a front side of the die; a molding material around the die; and a redistribution structure, where the die connectors of the die are attached to a first side of the redistribution structure, where the redistribution structure includes: a dielectric layer; a conductive line extending along a first surface of the dielectric layer facing the die; and a warpage tuning layer contacting and extending along a first surface of the conductive line facing the die, where a first coefficient of thermal expansion (CTE) of the conductive line is smaller than a second CTE of the warpage tuning layer.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Inventors: Chieh-Lung Lai, Meng-Liang Lin, Hsien-Wei Chen, Shin-Puu Jeng
  • Patent number: 11908764
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Liang Lin, Po-Yao Chuang, Te-Chi Wong, Shuo-Mao Chen, Shin-Puu Jeng
  • Patent number: 11901279
    Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Yi-Wen Wu, Po-Yao Chuang
  • Patent number: 11901277
    Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.
    Type: Grant
    Filed: July 3, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Yi-Wen Wu, Po-Yao Chuang
  • Publication number: 20240047401
    Abstract: A package structure is provided. The package structure includes an interposer substrate including an insulating structure, a conductive pad, a first conductive line, and a first conductive via structure. The package structure includes an electronic device bonded to the conductive pad. The package structure includes a chip structure bonded to the first end portion of the first conductive via structure. The package structure includes a first conductive bump connected between the chip structure and the first end portion of the first conductive via structure. The first end portion protrudes into the first conductive bump and is in direct contact with the first conductive bump.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Liang LIN, Po-Yao CHUANG, Shin-Puu JENG
  • Publication number: 20240030199
    Abstract: An embodiment semiconductor device includes an interposer, a semiconductor die electrically connected to the interposer, an integrated passive device die electrically connected to the interposer, the integrated passive device die including two or more seal rings, and a first alignment mark formed on the integrated passive device die within a first area enclosed by a first one of the two or more seal rings. The integrated passive device die may further include two or more integrated passive devices located within respective areas enclosed by respective ones of the two or more seal rings. Each of the two or more integrated passive devices may include electrical connections that are formed as a plurality of micro-bumps, and the first alignment mark may be electrically isolated from the electrical connections, and the first alignment mark and the electrical connections may share a common material.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Inventors: Hsien-Wei Chen, Chun Huan Wei, Meng-Liang Lin, Shin-Puu Jeng
  • Publication number: 20240014115
    Abstract: A semiconductor structure includes an interposer including redistribution wiring interconnects and redistribution insulating layers; a first semiconductor die attached to the interposer through a first array of solder material portions; and a second semiconductor die attached to the interposer through a second array of solder material portions. The interposer includes at least one inductor structure located between an area of the first array of solder material portions and an area of the second array of solder material portions in a plan view and laterally encloses a respective area in the plan view.
    Type: Application
    Filed: July 5, 2022
    Publication date: January 11, 2024
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Shin-Puu Jeng
  • Patent number: 11854955
    Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Patent number: 11855059
    Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
  • Publication number: 20230402403
    Abstract: A semiconductor package includes an interconnect structure, a plurality of dies disposed on the interconnect structure in a side-by-side manner, an underfill filling between the interconnect structure and the plurality of dies and filling a lower part of a gap between adjacent two of the plurality of dies, a conductive layer at least covering back surfaces of the adjacent two of the plurality of dies and filling an upper part of the gap, and an encapsulating material laterally encapsulating the plurality of dies and the conductive layer.
    Type: Application
    Filed: May 17, 2022
    Publication date: December 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Kuan Liang Liu, Shin-Puu Jeng
  • Publication number: 20230395581
    Abstract: A package is provided in accordance with some embodiments. The package includes a substrate including a first conductive via embedded in a first substrate core; a conductive pattern disposed on the first substrate core, wherein the conductive pattern includes a first conductive pad and a second conductive pad; a second substrate core disposed on the first substrate core and the conductive pattern; and a second conductive via disposed in the second substrate core and on the second conductive pad. The package also includes an encapsulant embedded in the second substrate core and in physical contact with the first conductive pad; a first die, including die connectors, embedded in the encapsulant and disposed on the first conductive pad; a redistribution structure disposed on the second conductive via, the die connectors and the encapsulant; and a second die disposed on the redistribution structure.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Shin-Puu Jeng
  • Publication number: 20230395521
    Abstract: An interposer for a semiconductor package and a method of fabricating an interposer including a peripheral metal pad surrounding an alignment mark. The alignment mark and the surrounding peripheral metal pad are formed on a first dielectric material layer of the interposer. A second dielectric material layer is located over the first dielectric material layer and at least partially over the peripheral metal pad structure and includes an recess extending around a periphery of the alignment mark. A third dielectric material layer is located over the second dielectric material layer and extends into the recess and contacts the alignment mark, the first dielectric material layer, and optionally a portion of the peripheral metal pad. The peripheral metal pad may enhance the adhesion between the first, second and third dielectric material layers near the alignment mark structure and thereby reduce the likelihood of crack formation.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Shin-Puu Jeng