Patents by Inventor Meng-Liang Lin

Meng-Liang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250253253
    Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.
    Type: Application
    Filed: April 22, 2025
    Publication date: August 7, 2025
    Inventors: Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong
  • Publication number: 20250253252
    Abstract: A semiconductor device structure includes a package substrate having a first side and a second side, a first stacking via formed within the package substrate, a second stacking via formed within the package substrate, and a first semiconductor die attached to the first side of the package substrate and electrically coupled to the first stacking via. The semiconductor device structure includes a second semiconductor die attached to the first side of the package substrate and electrically coupled to the second stacking via; and a bridge die attached to the second side of the package substrate and electrically coupled to the first stacking via and the second stacking via through first stacking via, the bridge die, and the second stacking via.
    Type: Application
    Filed: April 22, 2025
    Publication date: August 7, 2025
    Inventors: Hsien-Wei CHEN, Meng-Liang LIN, Shin-Puu JENG
  • Patent number: 12354989
    Abstract: A package structure is provided. The package structure includes an interposer substrate including an insulating structure, a conductive pad, a first conductive line, and a first conductive via structure. The package structure includes an electronic device bonded to the conductive pad. The package structure includes a chip structure bonded to the first end portion of the first conductive via structure. The package structure includes a first conductive bump connected between the chip structure and the first end portion of the first conductive via structure. The first end portion protrudes into the first conductive bump and is in direct contact with the first conductive bump.
    Type: Grant
    Filed: October 17, 2023
    Date of Patent: July 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Patent number: 12354938
    Abstract: A semiconductor package, which may correspond to a high-performance computing package, includes an interposer over a substrate. A spacer structure is mounted to a bottom surface of the interposer. The spacer structure is configured to maintain a clearance between a bottom surface of an integrated circuit die mounted to the bottom surface of the interposer and a top surface of the substrate to reduce a likelihood of an interference or collision between the integrated circuit die and the substrate. In this way, a likelihood of damage to the integrated circuit die and/or the substrate is reduced. Additionally, a robustness of an electrical connection between the integrated circuit die and the interposer may increase to improve a reliability and/or a yield of the semiconductor package including the spacer structure.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: July 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Shin-Puu Jeng
  • Patent number: 12300592
    Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Publication number: 20250132214
    Abstract: A semiconductor package includes a chiplet, a first underfill surrounding the chiplet, and a first encapsulant laterally covering the first underfill. The chiplet includes a semiconductor substrate and die connectors disposed over the semiconductor substrate. The first underfill includes first fillers, and a portion of the first fillers has a substantially planar surface at a first surface of the first underfill. The first encapsulant includes a first surface and a second surface opposite to the first surface, the first surface is substantially leveled with surfaces of the die connectors, and the second surface is substantially leveled with the first surface of the first underfill.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 24, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Ying-Ju Chen, Shin-Puu Jeng
  • Publication number: 20250132296
    Abstract: A semiconductor package includes an interposer including a first redistribution structure, a first semiconductor die electrically coupled to the first redistribution structure through conductive joints, and a first encapsulant disposed on the first redistribution structure and laterally covering the first semiconductor die. The first semiconductor die includes a semiconductor substrate including a first side facing the first redistribution structure and a second side opposite to the first side, a through substrate via provided within the semiconductor substrate, and a passive device disposed between the second side of the semiconductor substrate and the conductive joints.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 24, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Shin-Puu Jeng
  • Publication number: 20250105080
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.
    Type: Application
    Filed: December 11, 2024
    Publication date: March 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Liang Lin, Po-Yao Chuang, Te-Chi Wong, Shuo-Mao Chen, Shin-Puu Jeng
  • Publication number: 20250087564
    Abstract: Semiconductor packages and methods of fabricating semiconductor packages include an interposer, at least one semiconductor integrated circuit (IC) die mounted on a first surface of the interposer, a package substrate bonded to a second surface of the interposer, and a molding portion contacting the second surface of the interposer and laterally surrounding the package substrate. The package substrate may be laterally-confined with respect to the interposer such that at least one horizontal dimension of the package substrate may be less than the corresponding horizontal dimension of the interposer. In various embodiments, reliability of the bonding connections between the interposer and the package substrate may be improved thereby providing increased yields and improved package performance.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Ying-Ju Chen, Shin-Puu Jeng
  • Publication number: 20250079428
    Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.
    Type: Application
    Filed: November 15, 2024
    Publication date: March 6, 2025
    Inventors: Yi-Wen Wu, Po-Yao Chuang, Meng-Liang Lin, Techi Wong, Shih-Ting Hung, Po-Hao Tsai, Shin-Puu Jeng
  • Publication number: 20250062245
    Abstract: A semiconductor structure includes a circuit substrate, at least one semiconductor package, at least one semiconductor device, and a ring structure. The at least one semiconductor package is disposed on the circuit substrate, and the semiconductor package includes a plurality of integrated circuit structures. The at least one semiconductor device, disposed on the circuit substrate and aside the semiconductor package. The ring structure is disposed on the circuit board. The ring structure includes at least one opening pattern corresponding to the semiconductor device.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Ying-Ju Chen, Shin-Puu Jeng
  • Publication number: 20250054906
    Abstract: A semiconductor device includes an interposer, a first die, a second die, a third die and a dummy die. The interposer includes a first region and a second region. The first die and the second die are bonded to a first surface of the interposer, the first die is disposed in the first region, and the second die is disposed in the second region. The third die and the dummy die are bonded to a second surface opposite to the first surface of the interposer, wherein the third die is disposed in the first region and the dummy die is disposed in the second region.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Fu Fan, Shin-Puu Jeng
  • Publication number: 20250046722
    Abstract: A semiconductor package, which may correspond to a high-performance computing package, includes an integrated circuit die electrically and/or mechanically connected to a top surface of an interposer and a plurality of connection structures electrically and/or mechanically connected to a bottom surface of the interposer. The top surface of the interposer includes a set of test contact structures (e.g., one or more test bumps) that are electrically connected to the integrated circuit die through traces of the interposer. The set of test structures may be contacted by a probe needle to test a quality and/or a reliability of the integrated circuit die, as well as verify that traces of the interposer are functional. The set of test contact structures allows the integrated circuit die and traces of the interposer to be tested without probing the connection structures.
    Type: Application
    Filed: October 24, 2024
    Publication date: February 6, 2025
    Inventors: Hsien-Wei CHEN, Meng-Liang LIN, Shin-Puu JENG
  • Patent number: 12205861
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Liang Lin, Po-Yao Chuang, Te-Chi Wong, Shuo-Mao Chen, Shin-Puu Jeng
  • Patent number: 12199084
    Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
  • Publication number: 20250006572
    Abstract: A package structure includes a package substrate, a semiconductor die module on the package substrate, a first adhesive and a second adhesive on the package structure, wherein the second adhesive is between the first adhesive and the semiconductor die module, and a ring structure on the package substrate around the semiconductor die module, wherein the ring structure includes an outer ring attached to the package substrate by the first adhesive, and an inner ring between the semiconductor die module and the outer ring and attached to the package substrate by the second adhesive.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Ying-Ju Chen, Shin-Puu Jeng
  • Patent number: 12176337
    Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Wen Wu, Po-Yao Chuang, Meng-Liang Lin, Techi Wong, Shih-Ting Hung, Po-Hao Tsai, Shin-Puu Jeng
  • Publication number: 20240413034
    Abstract: A semiconductor device includes a bottom die including a first semiconductor layer, and a first redistribution layer (RDL) disposed on a bottom surface of the first semiconductor layer; a top die disposed on a top surface of the first semiconductor layer and including a second semiconductor layer, and a second RDL disposed on the top surface of the first semiconductor layer; a stress control (SC) layer disposed on the top surface of the first semiconductor layer and side surfaces of the first die; and a dielectric layer disposed on the SC layer, wherein the SC layer is configured to apply a compressive stress of at least ?100 MPa to the top surface of the first semiconductor layer, or the SC layer is configured to apply a tensile stress of at least 100 MPa to the top surface of the first semiconductor layer.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Inventors: Chieh-Lung Lai, Meng-Liang Lin, Hsien-Wei Chen, Shin-Puu Jeng
  • Patent number: 12165980
    Abstract: A semiconductor package, which may correspond to a high-performance computing package, includes an integrated circuit die electrically and/or mechanically connected to a top surface of an interposer and a plurality of connection structures electrically and/or mechanically connected to a bottom surface of the interposer. The top surface of the interposer includes a set of test contact structures (e.g., one or more test bumps) that are electrically connected to the integrated circuit die through traces of the interposer. The set of test structures may be contacted by a probe needle to test a quality and/or a reliability of the integrated circuit die, as well as verify that traces of the interposer are functional. The set of test contact structures allows the integrated circuit die and traces of the interposer to be tested without probing the connection structures.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Shin-Puu Jeng
  • Publication number: 20240395610
    Abstract: Vertically stacked semiconductor devices and methods of fabrication thereof that include a first semiconductor die bonded to a second device structure in a face-down configuration, a gap fill dielectric layer laterally surrounding the first semiconductor die, and a recess fill dielectric layer formed over the gap fill dielectric layer to fill concave recess defects in the gap fill dielectric that may result from cracks in the first semiconductor die. The recess fill dielectric layer may fill the entire volume of one or more concave recess defects in the gap fill dielectric material to a vertical depth of 5 ?m or more below the backside surface of a semiconductor substrate of the first semiconductor die. Providing a recess fill dielectric layer within concave recess defects in the gap fill dielectric layer may result in enhanced protection against electrical arcing during subsequent processing steps and thereby provide improved device yields.
    Type: Application
    Filed: May 25, 2023
    Publication date: November 28, 2024
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Ying-Ju Chen, Shin-Puu Jeng